Programmable Logic Devices:Dynamic PLA.

Dynamic PLA

If we want to realize a PLA in CMOS, instead of static nMOS circuit that has been discussed in Chapter 33, Section 33.3, in order to save power consumption, then a PLA in CMOS requires a large area because we need pMOS and nMOS subcircuits. Thus, instead of static CMOS, the dynamic CMOS illustrated in Figure 45.5(a) is usually used. During the absence of a clock pulse of the first- and second-phase clocks, φ1 and φ2 (i.e., during φ1 = φ2 = 0 (low voltage, using positive logic)) shown in Figure 45.5(b), pMOSFETs, T1, T2, and T3, become conductive and nMOSFETs, T4, T5, and T6 become non-conductive precharging vertical lines, P1, P2, and P3. When a clock pulse of the first-phase clock, φ1, appears but a clock-pulse of the second-phase clock, φ2, does not appear yet, i.e., when φ1 = 1 (high voltage) and φ2 = 0, pMOSFETs, T1, T2, and T3, become non-conductive and nMOSFETs, T4, T5, and T6, become conductive. Then, depending on the values of x, y, and z, some verticle lines, P1, P2, and P3 are discharged through some of the nMOSFETs in the AND array. (For example, if y = 0 (low voltage), P1 is discharged through nMOSFETs A.) A clock pulse of the second-phase clock, φ2, is still absent (i.e., φ2 = 0), so pMOSFETs, T7, T8, and T9, become conductive and nMOSFETs T10, T11, and T12, become non-conductive, precharging horizontal lines, f1, f2, and f3. When a clock pulse of the first-phase clock, φ1, is still present, and a clock pulse of the second-phase clock, φ2, appears, i.e., when φ1 = φ2 = 1, pMOSFETs, T7, T8, and T9, become non-conductive and nMOSFETs,T10, T11, and T12, become conductive. Then, some of horizontal lines, f1, f2, and f3, are discharged through some of the nMOSFETs in the OR array, depending on which of the vertical lines, P1, P2, and P3, are still charged.