Sequential Networks:Flip-Flops and Latches.

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Introduction

A logic network is called a sequential network when the values of its outputs depend not only on the current values of inputs but also on some of the past values, whereas a logic network is called a combinational network when the values of its outputs depend only on the current values of inputs but not on any past values. Analysis and synthesis of sequential networks are far more complex than combinational networks. When reliable operation of the networks is very important, the operations of logic gates are often synchronized by clocks. Such clocked networks, whether they are combinational or sequential networks, are called synchronous networks, and networks without clock are called asynchronous networks.

Flip-Flops and Latches

Because in a sequential network the outputs assume values depending not only on the current values but also on some past values of the inputs, a sequential network must remember information about the past values of its inputs. Simple networks called flip-flops that are realized with logic gates are usually used as memories for this purpose. Semiconductor memories can also serve as memories for sequential networks, but flip-flops are used if higher speed is necessary to match the speed of logic gates. Let us explain the simplest flip-flops, which are called latches.

S-R Latches

The network in Figure 31.1(a) which is called an S-R latch, consists of two NOR gates. Assume that the values at terminals S and R are 0, and the value at terminal Q is 0 (i.e., S = R = 0 and Q = 0). Since gate 1 has inputs of 0 and 0, the value at terminal Q is 1 (i.e., Q = 1). Since gate 2 in the network has two inputs, 0 and 1, its output is Q = 0. Thus, signals 0 and 1 are maintained at terminals Q and Q , respectively, as long as S and R remain 0. Now let us change the value at S to 1. Then, Q is changed to 0, and Q becomes 1 after a short time delay. Even if Q = 1 and Q = 0 were their original values, the change of the value at S to 1 still yields Q = 1 and Q = 0. In other words, Q is set to 1 by supplying 1 to S, no matter whether we originally had Q = 0, Q = 1, or Q = 1, Q = 0. Similarly, when 1 is supplied to R with S remaining at 0, Q and Q are set to 0 and 1, respectively, after a short time delay, no matter what values they had before. Thus, we get the first three combinations of the values of S and R shown in the table in Figure 31.1(b). In other words, as long as S = R = 0, the values of Q and Q are not changed. If S = 1, Q is set to 1. If R = 1, Q is set to 0. Thus, S and R are called set and reset terminals, respectively. In order to let the latch work properly, the value 1 at S or R must be maintained until new values of Q and Q are established. The S-R latch is usually denoted as in Figure 31.1(c). An S-R latch can also be realized with NAND gates, as shown in Figure 31.1(d). Latches and flip-flops have a direct reset-input terminal and a direct set-input terminal, although these input terminals are omitted in Figure 31.1 and in the figures for other flip-flops for the sake of simplicity. These input terminals are convenient for initial setting to Q = 1, or resetting to Q = 0.

When S = R = 1 occurs, the outputs Q and Q are both 0. If S and R simultaneously return to 0, these two outputs cannot maintain 0. Actually, a simultaneous change of S and R to 0 or 1 is physically impossible, often causing the network to malfunction, unless we make the network more sophisticated, such as synchronization of logic gates by a clock, as will be explained later. If S returns to 0 from 1 before R does, we have Q = 0 and Q = 1. If R returns to 0 from 1 before S does, we have Q = 1 and Q = 0.

Thus, it is not possible to predict what values we will have at the outputs after having S = R = 1. The output of this network is not defined for S = R = 1, as this combination is not used. For simplicity, let us assume that only one of the inputs to any network changes at a time, unless otherwise noted. This is a reasonable and important assumption.

Logic Synthesis with AND and OR Gates in Two Levels-0380

Flip-Flops

Usually, S-R latches are used in designing asynchronous sequential networks, although sequential networks can be designed without them. For example, the memory function can be realized with longer loops of gates than the loop in the latch, and also more sophisticated flip-flops than S-R latches can be used. For example, a loop consisting of a pair of inverters and a special gate called a transmission gate is used in CMOS networks, as we will see in Chapter 39, Section 39.2. But for synchronous networks, raceless flip-flops (described later in this chapter) are particularly important.

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