Dynamic Random Access Memory:Read/Write Circuit.

Read/Write Circuit

As shown in the previous section, the readout process is destructive because the resulting voltage of the cell capacitor Cs will no longer be (VDD – Vt) or 0 V. Thus, the same data must be amplified and written to the cell in every readout process.

Next to the storage cells, a sense amplifier with positive feedback structure, as shown in Figure 55.7, is the most important component in a memory chip to amplify the small readout signal in the readout process. The input and output nodes of the differential positive feedback sense amplifier are connected to the bit-lines BL and BL. The small readout signal appearing between BL and BL is detected by the differential sense amplifier and amplified to a full-voltage swing at BL and BL. For example, if the DRAM memory cell in BL has a stored data “1”, then a small positive voltage DV(1) will be generated and added to the bit-line BL voltage after the readout process. The voltage in the bit-line BL will be DV(1) + VDD/2. In the same time, the bit-line BL will keep its previous precharged voltage level, which is precharged to VDD/2. Thus, the small positive voltage DV(1) appears between BL and BL, with VBL higher than VBL, immediately after the readout process. It is amplified by the differential sense amplifier. The waveforms of VB before and after activating the sense amplifier are shown in Figure 55.8. After the sensing and restoring operations, the voltage VBL rises to VDD, and the voltage VBL falls to 0 V. The output at BL is then sent to the DRAM output pin.

The various circuits for read, write precharge, and equalization function are shown in Figure 55.9. The sequence of the read operation is performed as follows.

1. Initially, both the bit-lines BL and BL are precharged to VDD/2 and equalized before the data readout process. The precharge and equalizer circuits are activated by rising the control signal Fp. This will cause the bit-lines BL and BL to be at equal voltage. The control signal Fp goes low after the precharge and equalization.

2. The signal WL is selected by the row decoder. It goes up to connect the storage cell to the bit- lines BL and BL. A small voltage difference then appears between the bit-lines. The voltage level of the word-line signal WL can be greater than VDD to overcome the threshold voltage drop of the n-channel MOSFET transistor. Thus, the stored voltage level of data “1” at the memory cell can be raised to VDD.

3. Once a small voltage difference is generated between the bit-lines BL and BL by the storage cell, the differential sense amplifier is turned on by pulsing the sense control signal Fs high and the sense control signal Fs low. Then, the small voltage difference is amplified by the differential sense amplifier. The voltage levels in BL and BL will quickly move to VDD or 0 V by the regenerative action of the positive feedback operation in the differential sense amplifier.

4. After the readout sensing and restoring operations, the voltage levels of the bit-lines have a full voltage swing. Then the differential voltage levels at the bit-lines are read out to the differential output lines O and O, through a read circuit. A main sense amplifier is used to read and to amplify the output- lines. After these processes, the output data is selected and transferred to the output buffer.

In the write mode, the write control signal WRITE is activated. Selected bit-lines BL and BL are connected to a pair of input data controlled by the write control and write driver. The write circuit drives the voltage levels at the bit-lines to VDD or 0 V, and the data are transferred to the DRAM cell when access transistor is turned on.