Programmable Logic Devices:PLAs and Variations

Introduction

Hardware realization of logic networks is generally very time-consuming and expensive. Also, once logic functions are realized in hardware, it is difficult to change them. In some cases, we need logic networks that are easily changeable. One such case is logic networks whose output functions need to be changed frequently, such as control logic in microprocessors, or logic networks whose outputs need to be flexible, such as additional functions in wrist watches and calculators. Another case is logic networks that need to be debugged before finalizing. Programmable logic devices (i.e., PLDs) are for this purpose. On these PLDs, all transistor circuits are laid out on IC chips prior to designers’ use, considering all anticipated cases. With PLDs, designers can realize logic networks on an IC chip, by only deriving concise logic expressions such as minimal sums or minimal products, and then making connections among pre-laid logic gates on the chip. So, designers can realize their own logic networks quickly and inexpensively using these pre-laid chips, because they need not design logic networks, transistor circuits, and layout for each design problem. Thus, designers can skip substantial time of months for hardware design. CAD programs for deriving minimal sums or minimal products are well developed [1], so logic functions can be realized very easily and quickly as hardware, using these CAD programs. The ease in changing logic functions without changing hardware is just like programming in software, so the hardware in this case is regarded as “programmable.” Programmable logic arrays (i.e., PLAs) and FPGAs are typical programmable logic devices.

PLDs consists of mask-programmable PLDs and field-programmable PLDs. Mask-programmable PLDs (i.e., MPLDs) can be made only by semiconductor manufacturers because connections are made by custom masks. Manufacturers need to make few masks for connections out of all of more than 20 masks, according to customer’s specification on what logic functions are to be realized. Unlike mask- programmable PLDs, field-programmable PLDs (i.e., FPLDs) can be programmed by users and are economical only for small production volume, whereas MPLDs are economical for high production volume. Logic functions can be realized quicker on FPLDs than on MPLDs, saving payment of charges for custom masks for connections to semiconductor manufacturers, but they are larger, more expensive, and slower because of addition of electronic circuits for programmability.

Classification of PLDs is somewhat confusing in publications. Gate arrays to be described in Chapter 46 are regarded as PLDs in a broad sense in some publications, as shown in the following table, though PLDs may not include field-programmable gate arrays (i.e., FPGAs) in some publications. Field-programmable PLDs and FPGAs, are regarded as FPGAs in a broad sense. FPGAs in some cases have arrays of PLDs inside and are sometimes called complex PLDs to differentiate them from PLDs which are simpler.

PLAs and Variations

Programmable logic arrays (i.e., PLAs) are one of programmable logic devices. Logic functions realized in PLAs can be as easily changed as software is.

A programmable logic array (abbreviated as PLA), which was devised by Proebsting [9], is a special type of ROM (which stands for Read-Only Memory), although its usage is completely different from that of ROMs. MOSFETS are arranged in a matrix on a chip, as illustrated in Figure 45.1(a). A PLA consists of an AND array and an OR array. In order to store logic expressions, connections between the MOSFET gates and the vertical lines in the AND array and also connections between the MOSFET gates and the horizontal lines in the OR array are set up by semiconductor manufacturers during fabrication according to customer’ specifications. Since for these connections only one mask out of many necessary masks needs to be custom-made, PLAs are inexpensive when the production volume is high enough to make the custom preparation cost of the connection mask negligibly small. Because of low cost and design flexibility, PLAs are extensively used in VLSI chips, such as microprocessor chips for general computation and microcontroller chips for home appliances, toys, and watches.

When MOSFET gates are connected, as denoted by the large dots in Figure 45.1(a), we have, xy z , xz , xyz , at the outputs P1, P2, P3 of the AND array, respectively, since P1, P2, and P3 represent the outputs of NAND gates, if negative logic is used with n-MOS. Here, negative logic, where a high voltage and a low voltage are regarded as signal 0 and 1, respectively, is used for the sake of the convenience in deriving sums-of- products, i.e., disjunctive forms for the output functions f1, f2, and f3. (If positive logic is used, where a high voltage and a low voltage are regarded as signal 1 and 0, respectively, then P1, P2, and P3 represent the outputs of NOR gates, and f1, f2, and f3 are expressed in the forms of product-of-sums, i.e., in conjunctive forms. Since most people prefer disjunctive forms, negative logic is usually used in the case of PLAs.) Then, the outputs f1, f2, and f3 of the OR-array also represent the outputs of NAND gates with P1, P2, P3 as their inputs. Thus,

(It is to be noted that in the AND array, the inputs x, y, and z have their complements by inverters.) Therefore, the two arrays in Figure 45.1(a) represent a network of NAND gates in two levels, as illustrated in Figure 45.1(b). This can be redrawn in Figure 45.1(c) by moving the bubbles (i.e., inverters) to the inputs of the NAND gates 4, 5, and 6 without changing the outputs f1, f2, and f3. Then, gate 4, for example, can be replaced by an OR gate because f1 is

by De Morgan’s theorem. Thus, this is interpreted as a network of AND gates in the first level and OR gates in the second (output) levels, as illustrated in Figure 45.1(d). This is the reason why the upper and lower matrices in Figure 45.1(a) are called AND and OR arrays, respectively. The vertical lines which run through the two arrays in Figure 45.1(a) are called the product lines, since they correspond to the product terms in disjunctive forms for the output functions f1, f2, and f3. Thus, any combinational network (or networks) of AND and OR gates in two levels can be realized by a PLA. The connections of MOSFET gates to horizontal or vertical lines are usually denoted by dots, as shown in Figure 45.2.

Sequential networks can also be easily realized on a PLA, as shown in Figure 45.2. Some outputs of the OR array are connected to the inputs of master-slave flip-flops (usually J-K master-slave flip-flops), whose outputs are in turn connected to the AND array as its inputs. More than one sequential network can be realized on a single PLA, along with many combinational networks. Flip-flops can be also realized inside the AND and OR arrays without providing them outside the arrays.

In many PLAs, the option of an output f1 or its complement f1 is provided in order to give flexibility, as illustrated in the lower right-hand corner of Figure 45.2. By disconnecting one of the two ×’s at each output, we can have either f1 or f1 as output, as illustrated in Figure 45.3. W hen f1 has too many products in its disjunctive form and cannot be realized on a PLA, its complement f1 may have a sufficiently small number of terms to be realizable on the PLA, or vice versa.

If the number of product lines in a PLA is too many, each horizontal line gets too long with a significant increase in parasitic capacitance. Then, if the majority of the MOSFET gates provided are connected to this horizontal line, the input or its inverter has too many fan-out connections on this horizontal line. Similarly, the total number of horizontal lines cannot be too large. In other words, the array size of a PLA is limited because of speed considerations. In contrast, the size of a ROM can be much larger, since we can use more than one decoder, or use a complex decoding scheme.

The PLAs whose connections of some MOSFETs to lines are made by custom masks by semiconductor manufacturers are called mask-programmable PLAs (abbreviated as MPLAs).

A field-programmable PLA (abbreviated as FPLA) is also available, using fuses or anti-fuses, where unlike fuses, anti-fuses are initially not connected but can be connected by applying a voltage that is higher than a normal voltage. In an FPLA, a user can set up a dot pattern by blowing fuses or connecting anti-fuses connected to some MOSFETs by temporarily feeding excessively high voltages. In this realiza- tion, a special electronic circuit to blow fuses or to connect anti-fuses must be provided in addition to the PLA arrays, and this adds extra area to the entire area. In large-volume production, FPLAs are more expensive due to this extra size than PLAs, but when users need a small number of PLAs, FPLAs are much cheaper and convenient, since users can program FPLAs by themselves, inexpensively and quickly, instead of waiting weeks for the delivery of MPLAs from semiconductor manufacturers.

In contrast to the above FPLAs based on fuses, FPLAs whose undesired connections are disconnected by laser beam are also available. In this case, the chip size is smaller than that of the above FPLAs, since the electronic circuits to blow fuses are not necessary, but special laser equipment is required.

FPLAs are less expensive than MPLAs for small production volumes, although for high production volumes, MPLAs are much less expensive. In particular, when designers want to use MPLAs but their design is not completely debugged, they should try their design ideas with FPLAs and then switch to MPLAs only after debugging is complete, because if a semiconductor manufacturer is already working on MPLAs, sudden interruption of the work due to the discovery of design mistakes is unprofitable for both the manufacturer and the customer.