Multipliers:Array Multiplier

Array Multiplier

The simplest parallel multiplier is an array multiplier [2] in which the multiplicand-multiples (i.e., (yj · X)’s) are summed up one by one by means of a series of carry save adders. It has a two-dimensional array structure of full adders as shown in Figure 42.3. Each row of full adders except the bottom one forms a carry save adder. The bottom row forms a ripple carry adder for the final carry propagate addition. An array multiplier is suited for VLSI realization because of its regular cellular array structure. The number of logic gates is proportional to n2. The delay is proportional to n.

We can reduce the delay in the final adder by using a faster carry propagate adder such as a carry select adder. Also, we can reduce the delay in the array part in Figure 42.3 by means of 2-bit Booth’s method mentioned in Section 42.2. Since 2-bit Booth’s method reduces the number of multiplicand-multiples to about half, the number of necessary carry save additions is also reduced to about half, and hence, the delay in the array part is reduced to about half. But the amount of hardware is not reduced much because a 2-bit Booth recoder and multiplicand-multiple generators, which essentially work as selectors, are required.

Another method to reduce the delay in the array part is to double the accumulation stream [6]. Namely, we divide the multiplicand-multiples into two groups, sum up the members of each group by a series of carry save adders independently of the other group, and then sum up the two accumulations into one. The delay in the array part is reduced to about half. The 2-bit Booth’s method can be combined with this method. We can further reduce the delay by increasing the number of accumulation streams, although it complicates the circuit structure.