Cell-Library Design Approach:Hierarchical Design Approach.

Hierarchical Design Approach

The cell library design approaches, using cells of different shapes and sizes, can reduce the chip size more than the polycell design approach, because by keeping the same height, a large portion of the area of each cell is wasted, and by keeping all connections among cells in routing channels, the connection area may not be minimized. Moreover, by using a hierarchical approach based on cells of different shapes and sizes—in other words, by treating many cells as a building block in a higher level, and many such building blocks as a building block in a next higher level, and so on—we can further reduce the chip area, as illustrated in Figure 48.2, because global area minimization can be treated better, even though this is done on the monitor. In other words, cells A, B, C, and D are assembled into a block R (shown in a dot-lined rectangle), as shown in Figure 48.2. Then, such blocks, R, S, T and U, shown in dot-lined rectangles are assembled into a bigger block W, which is a block in a higher level than blocks R, S, T, and U, as shown in Figure 48.2. But this is much more time-consuming than the polycell design approach, and the development of efficient CAD programs is harder. It appears to be difficult to make the difference of chip area from full-custom designed chips within about 20%, although the areas of full-custom designed chips vary greatly with designers and, accordingly, comparison is not simple.