Dynamic Random Access Memory:Concept of 2-Bit DRAM Cell.

Concept of 2-Bit DRAM Cell

The 2-bit DRAM is an important architecture in the multi-level DRAM. Let us discuss an example of a multi-level technique used for a 4-Gb DRAM by NEC [17]. Table 55.1 lists both the 2-bit/4-level storage concept and the conventional 1-bit/2-level storage concept. In the conventional 1-bit/2-level DRAM cell, the storage voltage levels are Vcc or GND, corresponding to logic values “1” or “0”. The signal charge is one half the maximum storage charge. In the 2-bit/4-level DRAM cell, the storage voltage levels are Vcc, two-thirds Vcc, one-third Vcc, and GND, corresponding to logic values “11”, “10”, “01”, and “10”, respectively. Three reference voltage levels are used to detect these four storage levels. Reference levels are positioned at the midlevel between the four storage levels. Thus, the signal charge between the storage and reference levels is one sixth of the maximum storage charge.

Sense and Timing Scheme

The circuit diagram of the 2-bit/4-level storage technique is shown in Figure 55.17. A pair of bit-lines is separated into two sections by transfer switches in order to have a capacitance ratio of two between Sections A and B.

Two sense amplifiers and two cross-coupled capacitors Cc are connected to each section. During the stand-by cycle, the transfer signal TG is high and the transfer switch is turned ON. The bit-lines are precharged to the half-Vcc level. As shown in Figure 55.17(b), at time T1, the circuit is operated in the active cycle, and a word-line is selected and the charge stored in the cell Cs is transferred to the bit-lines. At time T2, the transfer switches are turned OFF and the bit-lines are isolated. At time T3, the sense amplifier in Section A is activated and the bit-lines in Section A are driven to Vcc and GND, depending on the stored data. The amplified data in Section A is the most significant bit (MSB) of the stored data because the reference level is half-Vcc.

At the same time interval, the MSB is transferred to the bit-lines in Section B through a cross coupled capacitor Cc. It can change the bit-line level in Section B for subsequent least significant bit (LSB) sensing. At time T4, the sense amplifier in section B is activated and the LSB is sensed. At time T5, the transfer switch is turned ON, the charge on each bit-line is shared, and the read-out data is restored to the memory cell.

Charge-Sharing Restore Scheme

Table 55.2 lists the restored level generated by the charge-sharing restore scheme. The MSB is latched in Section A, and the LSB is latched in Section B. The capacitance ratio between Sections A and B is 2. The charge of the MSB and the charge of the LSB are combined on the bit-line, and the restore level Vrestore is generated.

Charge-Coupling Sensing

Figure 55.18 shows the charge in bit-line levels due to coupling capacitor Cc. The MSB is sensed using the reference level of half-Vcc, as mentioned earlier. The MSB generates the reference level for LSB sensing. When Vs is defined as the absolute signal level of data “11” and “00”, the absolute signal level of data “10” and “01” is one-third of Vs. Here, Vs is directly proportional to the ratio between storage capacitor Cs and bit-line capacitance.

In the case of sensing data “11”, the initial signal level is Vs. After MSB sensing, the bit-line level in Section B is changed for LSB sensing by the MSB through coupling capacitor Cc. The reference bit-line in Section B is raised by Vc, and the other bit-line is reduced by Vc. For LSB sensing, Vc is one-third of Vs due to the coupling capacitor Cc.

Using the two-step sensing scheme, the 2-bit data in a DRAM cell can be implemented.