CMOS:Logic Design in Differential CMOS Logic.

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Logic Design in Differential CMOS Logic
Differential CMOS logic is a logic gate that works very differently from the CMOS logic gate discussed so far. It has two outputs, f and its complement, f , and works like a flip-flop such that when one output is a high voltage, it always makes the other output have a low voltage.
A logic gate in cascode voltage switch logic, which is abbreviated as CVSL, is illustrated in Figure 39.6. CVSL is sometimes called differential logic because CVSL is a CMOS logic gate that realizes both an output function, f, and its complement, f , switching their values quickly. The CVSL gate shown in Figure 39.6(a) has a driver that is a tree consisting of nMOSFETs, where each pair of nMOSFETs in one level has input xi and its complement xi . The top end of each path in the tree expresses the complement of a minterm (just like series-gating ECL described in Chapter 38). Then by connecting some of these top ends to both the gate of one pMOSFET (i.e., P1), and the drain of the other pMOSFET (i.e., P2), we can realize the complement of a sum-of-products. The connection of the remaining top ends to both the gate of P2 and the drain of P1 realizes its complement. The outputs in Figure 39.6(a) realize

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When one path in the tree is conductive, the output of it, say the output f, has a lower voltage, and P1 (i.e., the pMOSFET whose gate is connected to f ) becomes conductive. Then, the other output f has a high voltage. The driver tree in Figure 39.6(a), which resembles series-gating ECL, can be simplified as shown in (b). (The tree structure in CSVL in (b) can be obtained from an ordered reduced binary decision diagram described in Chapters 26 and 29.) Notice that P1 and P2 in (a) are cross-connected for fast switching.

CVSL can be realized without tree structure. Figure 39.7 shows such a CSVL gate, for f = xy and its complement. The connection configuration of nMOSFETs connected to one output terminal is dual to that connected to the other output terminal (in Figure 39.7, nMOSFETs for the output terminal for f are

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CVSL has a variant called dynamic CVSL, to be described later. In order to differentiate from this, CVSL here is usually called static CVSL.

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