Dynamic Random Access Memory:DRAM Memory Cell

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DRAM Memory Cell

In early CMOS DRAM storage cell design, three-transistor and four-transistor cells were used in 1-Kb and 4-Kb generations. Later, a particular one-transistor cell, as shown in Figure 55.4(a), became the industry standard [5,6]. The one-transistor (1T) cell achieves smaller cell size and low cost. The cell consists of an n-channel MOSFET and a storage capacitor Cs. The charge is stored in the capacitor Cs and the n-channel MOSFET functions as the access transistor. The gate of the n-channel MOSFET is

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connected to the word-line WL and its source/drain is connected to the bit-line. The bit-line has a capacity CBL, including the parasitic load of the connected circuits.

The DRAM cell stores one bit of information as the charge on the cell storage capacitor Cs. Typical values for the storage capacitor Cs are 30 to 50 fF. When the cell stores “1”, the capacitor is charged to VDD – Vt. When the stores “0”, the capacitor is discharged to 0 V.

During the READ operation, the voltage of the selected word-line is high; the access n-channel MOSFET is turned on, thus connecting the storage capacitor Cs to the bit-line capacitance CBL as shown in Figure 55.4(b). The bit-line capacitance CBL, including the parasitic load of the connected circuits, is about 30 times larger than the storage capacitor Cs. Before the selection of the DRAM cell, the bit-line is precharged to a fixed voltage, typically VDD/ 2 [7]. By using the charge conservation principle, during the READ operation, the bit-line voltage changes by

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Since ratio R = CBL/Cs is large, these readout bit-line sense signals DV(1) and DV(0) are very small. Typical values for the sense signal are about 100 mv.

For low-voltage operation, the supply voltage VDD is reduced. Thus, a lower R ratio is required to maintain the sense signals to have enough margin against noise. The main approach is to use a large

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cell storage capacitor Cs. As shown in Figure 55.5, a conventional Cs was implemented by a simple planar-type capacitor. The charge storage in the cell takes place on both the poly-1 gate oxide and the depletion capacitances. The planar DRAM cells have been used in the 1-T DRAMs from the 16 kb to the 1 Mb. The limits of the planar DRAM cell for retaining sufficient capacitance were reached in the mid-1980s in the 1-Mb DRAM. With the increased density higher than 1 Mb, smaller horizontal geometry on the surface of the wafer can be achieved by making increased use of the vertical dimension [8]. One approach is to use a trench capacitor, as shown in Figure 55.6(a) [9]. It is folded vertically into the surface of the silicon in the form of a trench. Another approach for reducing horizontal

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capacitor size is to stack the capacitor Cs over the n-channel MOSFET access transistor, as shown in Figure 55.6(b).

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