Logic Synthesizer by the Transduction Method:Various Transduction Methods.

Various Transduction Methods

In addition to gate substitution, connectable/disconnectable conditions, generalized gate merging, and error compensation, outlined thus far, some known transformations can be generalized for efficient processing, using permissible functions. In the gate merging procedure, for example, a permissible function which is common to two gates, vi and vj, can be easily found. Without permissible functions, the transformations would be excessively time-consuming.

We can have different transduction methods by combining different transformations and the pruning procedure. In other words, we can have different transduction methods based on different orders in processing gates, connections, and components of MSPFs or CSPFs.

These transduction methods can be realized in Figure 37.2, which illustrates the basic structure of the transduction method outlined in Procedure 37.1. We can use these transduction methods in the following different manners:

1. An initial network can be designed by any conventional logic design method. Then we apply the transduction methods to such an initial network. The transduction methods applied to different initial networks usually lead to different final networks.

2. Instead of applying a transduction method only once, we can apply different transduction methods to an initial network in sequence. In each sequence, different or identical transduction methods can be applied in different orders. This usually leads to many different final networks.

Thus, if we want to explore the maximum potential of the transduction methods, we need to use them in many different ways, as explained in 1 and 2 [3,4].

Computational Example of the Transduction Method

Let us show a computational example of the transduction method. Suppose the initial network, which realizes a four-variable function, given as illustrated in Figure 37.15(a), and this function has a minimal network shown in Figure 37.15(b) (its minimality is proved by the integer programming logic design method). Beginning with the initial network of 12 gates shown in Figure 37.15(a), the transduction method with error-compensation transformation (this version was called NETTRA-E3) produced the tree of solutions shown in Figure 37.16. The size of the tree can be limited by the program parameter, NEPMAX [6]. (In Figure 37.16, NEPMAX was set to 2. If set to 8, we will have a tree of 81 networks). The notation “a/b:c” in Figure 37.16 means a network numbered a (numbered according to the order of generation), consisting of b gates and c connections, and a line connecting a larger network with a smaller one means that the smaller is derived, treating the larger as an initial network. In Figure 37.16, it is important to notice that while some paths lead to terminal nodes representing minimal networks, others lead to terminal nodes representing networks not very close to the minimal. By comparing the numbers of gates and connections in the networks derived at the terminal nodes of this solution tree, a best solution can be found.

Intermediate solutions are logic networks with different connection configurations of negative gates, so some of them may be more appropriate for layout than others.