Logic Synthesis with a Minimum Number of Negative Gates:Algorithm DIMN

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Algorithm DIMN

Compared with the problem (1) of Procedure 35.1, problem (2) presents a far more serious difficulty. Thus, Algorithm DIMN (an acronym for Design of Irredundant Minimal Network) was developed to design a MOS network in single-rail input logic such that the number of gates is minimized and every connection among cells is irredundant (i.e., if any connection among logic gates is removed, the network output will be changed) [2,3]. Algorithm DIMN is powerful but is far more complex than the minimal labeling procedure (i.e., Phases 1 and 2 of Procedure 35.1). So, let us only outline it.

Procedure 35.2: Outline of Algorithm DIMN

1. All the nodes of a lattice are labeled by the minimal labeling procedure (i.e., Phases 1 and 2 of Procedure 35.1), starting with the top node and moving downward. Let the number of bits of each label be R. Then all the nodes are labeled by a procedure similar to the minimal labeling procedure, starting with the bottom node which is now labeled with the largest binary number of R bits, and moving upward on the lattice. Then, the first negative gate with irredundant MOSFETs is designed after finding as many don’t-cares as possible by comparing two labels at each node which are derived by these downward and upward labelings.

2. The second negative gate with irredundant MOSFETs is designed after downward and upward labelings to find as many don’t-cares as possible. This process is repeated to design each gate until the network output gate with irredundant MOSFETs is designed. D Unlike the minimal labeling procedure where the downward labeling is done only once and then the entire network is designed, Algorithm DIMN repeats the downward and upward labelings for designing each negative gate. The network derived by DIMN for the function x1x2x3x4 ∨ x1x2x3x4 ∨ x1x2x3x4 ∨ x1x2x3x4 , for example, has three negative gates, the same as that of the network derived by the minimal labeling procedure for the same function. The former, however, has only 12 n-channel MOSFETs, whereas the latter has 20 n-channel MOSFETs. DIMN usually yields networks that are substantially simpler than those designed by the minimal labeling procedure, but it has the same problems as Procedure 35.1 when the number of input variables of the function becomes large.

The computational efficiency of DIMN was improved [4]. Also, a version of DIMN specialized to two- level networks was developed [1].

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