Logic Properties of Transistor Circuits:Transistor Circuits

Transistor Circuits

Bipolar transistor and MOSFET are currently the two most important types of transistors for integrated circuit chips, although MOSFET is becoming increasingly popular [2]. A transistor is made of pure silicon that contains a trace of impurities (i.e., n-type silicon or p-type silicon). When a larger amount of impurity than standard is added, we have n+- and p+-type silicon. When less, we have n–- and p–-type silicon. A bipolar transistor has a structure of n-type region (or simply n-region) consisting of n-type silicon and p-type region (or simply p-region) consisting of p-type silicon, as illustrated in Figure 33.7, different from that of MOSFET illustrated in Figure 33.10.

Bipolar Transistors

An implementation example of an n-p-n bipolar transistor, which has three electrodes (i.e., an emitter, a base, and a collector) is shown in Figure 33.7(a) along with its symbol in Figure 33.7(b). A p-n-p transistor has the same structure except p-type regions and n-type regions exchanged (n+- and p+-type regions also exchanged).

Suppose that an n-p-n transistor is connected to a power supply with a resistor and to the ground, as shown in Figure 33.8(a). When the input voltage vi increases, the collector current ic gradually increases, as shown in Figure 33.8(b). (Actually, ic is 0 until vi reaches about 0.6 V. Then ic gradually increases and then starts to saturate.) As ic increases, the output voltage v0 decreases from 5 V to 0.3 V or less because of the voltage difference across the resistor R, as shown in Figure 33.8(c). Therefore, when the input vi is a high voltage (about 5 V), the output v0 is a low voltage (about 0.3 V), and when vi is a low voltage (about 0.3 V),

v0 is a high voltage (about 5 V). This is illustrated in Table 33.3(a). Thus, if binary logic values 0 and 1 are represented by low and high voltages, respectively, we have the truth table in Table 33.3(b). This means that the circuit in Figure 33.8(a) works as an inverter. In other words, if vi represents a logic variable x, then v0 represents the logic function x .

Since we are concerned with binary logic values in designing logic networks, we will henceforth consider only the on-off states of currents or the corresponding voltages in electronic circuits (e.g., A and B in Figure 33.8(b), or A′ and B′ in Figure 33.8(c)), without considering their voltage magnitudes. As we will see later, the transistor circuit in Figure 33.8(a) is often used as part of more complex transistor circuits that constitute logic gates. Here, notice that if resistor R′ is added between the emitter and the ground, and the output terminal v0 is connected to the emitter, instead of to the collector, as shown in Figure 33.9, then the new circuit does not work as an inverter. In this case, when vi is a high voltage, v0 is also a high voltage, because the current that flows through the transistor produces the voltage difference across resistor R′. When vi is a low voltage, v0 is also a low voltage, because no current flows and consequently no voltage difference develops across R′. So if vi represents a variable x, v0 represents the logic function x, and no logic operation is performed. The transistor circuit in Figure 33.9, which is often called an emitter follower, works as a current amplifier. This circuit is used often as part of other circuits to supply a large output current by connecting the collector of the transistor directly to the Vcc without R.

A logic gate based on bipolar transistors generally consists of many transistors which are connected in a more complex manner than Figure 33.8 or 33.9, and realizes a more complex logic function than

x . (See Chapter 38 on ECL.)

MOSFET (Metal-Oxide Semiconductor Field Effect Transistor)

In integrated circuit chips, two types of MOSFETs are usually used; that is, n-channel enhancement- mode MOSFET (or abbreviated as n-channel enhancement MOS, or enhancement nMOS) and p-channel enhancement-mode MOSFET (or abbreviated as p-channel enhancement MOS, or enhancement pMOS). The structure of the former is illustrated in Figure 33.10(a). They are expressed by the symbols shown in Figure 33.10 (b) and (c), respectively. Each of them has three terminals: gate, source, and drain. In Figure 33.10(a), the gate realized with metal is shown for the sake of simplicity, but a more complex structure, called silicon-gate MOSFET, is now far more widely used. The “gate” in Figure 33.10 should not be confused with “logic gates.” The thin area underneath the gate between the source and drain regions in Figure 33.10(a) is called a channel, where a current flows whenever conductive.

Suppose that the source of an n-channel enhancement-mode MOSFET is grounded and the drain is connected to the power supply of 3.3 V through resistor R, as illustrated in Figure 33.11(a). When the

input voltage vi increases from 0 V, the current i, which flows from the power supply to the ground through R and the MOSFET, increases as shown in Figure 33.11(b), but for vi smaller than the threshold voltage VT , essentially no current flows. Then because of the voltage drop across R, the output voltage v0, decreases, as shown in Figure 33.11(c). Since we use binary logic, we need to use only two different voltage values, say 0.2 and 3.3 V. If vi is 0.2 V, no current flows from the power supply to the ground through the MOSFET and v0 is 3.3 V. If vi is 3.3 V, the MOSFET becomes conductive and a current flows. V0 is 0.2 V because of the voltage drop across R. Thus, if vi is a low voltage (0.2 V), v0 is a high voltage

V); and if vi is a high voltage, v0 is a low voltage, as shown in Table 33.4(a). If low and high voltages represent logic values 0 and 1, respectively, in other words, if we use positive logic, Table 33.4(a) is converted to the truth table in Table 33.4(b). (When low and high voltages represent 1 and 0, respectively, this is said to be in negative logic.) Thus, if vi represents logic variable x, output v0 represents function x . This means that the electronic circuit in Figure 33.11(a) works as an inverter.

Resistor R shown in Figure 33.11 occupies a large area, so it is usually replaced by a MOSFET, called an n-channel depletion-mode MOSFET, as illustrated in Figure 33.12, where the depletion-mode MOS- FET is denoted by the MOSFET symbol with double lines. Notice that the gate of this depletion-mode MOSFET is connected to the output terminal instead of the power supply, the logic gate with depletion-mode MOSFET replacing the resistor work in the same manner as before. Logic gates with depletion- mode MOSFETs work faster and are more immune to noise.

The n-channel depletion-mode MOSFET is different from the n-channel enhancement-mode MOSFET in having a thin n-type silicon layer embedded underneath the gate, as illustrated in Figure 33.13. When a positive voltage is applied at the drain against the source, a current flows through this thin n-type silicon layer even if the voltage at the gate is 0 V (against the source). As the gate voltage becomes more positive, a greater current flows. Or, as the gate voltage becomes more negative, a smaller current flows.

If the gate voltage decreases beyond threshold voltage VT , no current flows. This relationship, called a transfer curve, between the gate voltage VGS (against the source) and the current i is shown in Figure 33.14(a), as compared with that for the n-channel enhancement-mode MOSFET shown in Figure 33.14(b).

By connecting many n-channel enhancement MOSFETs, we can realize any negative function, i.e., the complement of a sum-of-products where only non-complemented literals are used ( x ∨ yz is an example of negative function). For example, if we connect three MOSFETs in series, including the one for resistor replacement, as shown in Figure 33.15, the output f realizes the NAND function of variables x and y. Only when both inputs x and y have high voltages, two MOSFETs for x and y become conductive and a current flows through them. Then the output voltage is low. Otherwise, at least one of them is non-conductive and no current flows. Then the output voltage is high. This relationship is shown in Table 33.5(a). In positive logic, this is converted to the truth table 33.5(b), concluding that the circuit represents xy

which is called

the NAND function. Figure 33.16 shows a logic circuit for x ∨ y (called the NOR function) by connecting MOSFETs in parallel. A more complex example is shown in Figure 33.17.

The MOSFET that is connected between the power supply and the output terminal is called a load or load MOSFET in each of Figure 33.15 through 33.17. Other MOSFETs that are directly involved in logic operations are called a driver or driver MOSFETs in each of these circuits.

Procedure 8.3: Calculation of the Logic Function of a MOS Logic Gate The logic function f for the output of each of these MOS logic gates can be obtained as follows.

1. Calculate the transmission of the driver, regarding each n-channel MOSFET as a make-contact of relay, as illustrated in Figure 33.18. When x = 1, a current flows through the magnet in the make-contact relay in Figure 33.18 and the contact x is closed and becomes conductive, whereas n-MOS becomes conductive when x = 1, i.e., input x of nMOS is a high voltage.

2. Complement it. D For example, the transmission of the driver in Figure 33.16 is x ∨ y. Then by complementing it, we have the output function f = x ∨ y. The output function of a more complex logic gate, such as Figure 33.18, can be calculated in the same manner. Thus, a MOS circuit expresses a negative function with respect to input variables connected to driver MOSFETs.

Difference in the Behavior of n-MOS and p-MOS Logic Gates As illustrated in Figure 33.19, an n-MOS logic gate behaves differently from a p-MOS logic gate. In the case of an n-MOS logic gate which consists of all nMOSFETs, illustrated in Figure 33.19(a), the power supply of the n-MOS logic gate must be positive voltage, say +3.3 V, whereas the power supply of the p-MOS logic gate which consists of all pMOSFETs, illustrated in Figure 33.19(b), must be a negative

voltage. Otherwise, these logic gates do not work. Each n-MOS in the driver in Figure 33.19(a) becomes conductive when a high voltage (e.g., +3.3 V) is applied to its MOSFET gate, and becomes non-conductive when a low voltage (e.g., 0 V) is applied to its MOSFET gate. A direct current flows to the ground from the power supply, as shown by the bold arrow when the driver becomes conductive. In contrast, each p-MOS in the driver in Figure 33.19(b) becomes non-conductive when a high voltage (e.g., 0 V) is applied to its MOSFET gate, and becomes conductive when a low voltage (e.g., –3.3 V) is applied to its MOSFET gate. A direct current flows to the power supply from the ground (i.e., in the opposite direction to the case of n-MOS logic gate in (a)), as shown by the bold arrow when the driver becomes conductive. The relationship among voltages at the inputs and outputs for these logic gates are shown in Figure 33.19(c) and (d). In positive logic, i.e., interpretation of a positive and negative voltages as 1 and 0, respectively, the table in Figure 33.19(c) yields the truth table for NOR, i.e., x ∨ y, shown in (e), and in negative logic, i.e., interpretation of a positive and negative voltages as 0 and 1 respectively, the table in (d) also yields the truth table for NOR in (e). Similarly, in negative logic, the table in Figure 33.19(c) yields the truth table for NAND, i.e., xy , shown in (f), and in positive logic, the table in (d) also yields the truth table for NAND in (f). The two functions in (e) and (f) are dual. The relationships in these examples are extended into the general statements, as shown in the upper part of Figure 33.19. Whether we use n-MOSFETs or p-MOSFETs in a logic gate, the output of the gate represents the same function by using positive or negative logic, respectively, or negative or positive logic, respectively. Thus, if we have a logic gate, realizing a function f, that consists of all n-MOS or all p-MOS, then the logic gate that is derived by exchanging n-MOS and p-MOS realizes its dual fd, no matter whether positive logic or negative logic is used.

The output function of a logic gate that consists of all p-MOS can be calculated by Procedure 33.3, regarding each p-MOS as a make-contact relay. But each p-MOS is conductive (instead of being non- conductive) when its gate voltage is low, and is non-conductive (instead of being conductive) when its gate voltage is high. Also the output of the p-MOS logic gate is high when its driver is conductive (in the case of the n-MOS logic gate, the output of the gate is low when its driver is conductive) and is low when its driver is non-conductive (in the case of the n-MOS logic gate, the output of the gate is high when its driver is non-conductive). In other words, the polarity of voltages at the inputs and output of a p-MOS logic gate is opposite to that of an n-MOS logic gate. Thus, by using negative logic, a p-MOS logic gate has the same output function as the n-MOS logic gate in the same connection configuration in positive logic, as illustrated in Figure 33.19.