Dynamic Random Access Memory:Synchronous (Clocked) DRAMs

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Synchronous (Clocked) DRAMs

The application of multimedia is a very hot topic nowadays, and the multimedia systems require high speed and large memory capacity to improve the quality of data processing. Under this trend, high density, high bandwidth, and fast access time are the key requirements of future DRAMs.

The synchronous DRAM (SDRAM) has the characteristic of fast access speed, and is widely used for memory application in multimedia systems. The first SDRAM appeared in the 16-Mb generation, and the current state-of-the-art product is a Gb SDRAM with GB/s bandwidth [10–14].

Conventionally, the internal signals in asynchronous (non-clocked) DRAMs are generated by “address transition detection” (ATD) techniques. The ATD clock can be used to activate the address decoder and driver, the sense amplifier, and the peripheral circuit of DRAMs. Therefore, the asynchronous DRAMs require no external system clocks and have a simple interface. However, during the asynchronous DRAM access cycle, the process unit must wait for the data from the asynchronous DRAM, as shown in Figure 55.10. Therefore, the speed of the asynchronous DRAM is slow.

On the other hand, the synchronous interface (clocked) DRAMs making it under the control of the edge of the system clock. The input addresses of a synchronous DRAM are latched into the DRAM, and the output data is available after a given number of clock cycles—during which the processor unit is free and does not wait for the data from the SDRAM, as shown in Figure 55.11. The block diagram of an

Dynamic Random Access Memory-0656

Dynamic Random Access Memory-0657

SDRAM is shown in Figure 55.12. With the synchronous interface scheme, the effective operation speed of a given system is improved.

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