System Level Design Languages:State Machine Diagram

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State Machine Diagram

A state machine diagram models the behavior of an object when different events happen at run-time. State machine diagrams include states and transitions.

States, in a state machine, illustrate the condition and status of objects. States are shown with a round-cornered rectangle. A state element in state machine diagrams can be another state machine diagram. In addition, there are a few pseudo-states which have special behaviors. Pseudo-states are shown in Figure 86.33 and Figure 86.34, and Figure 86.35 shows transition from state1 to state2. Figure 86.36(a) and Figure 86.36(b) are complete examples of state machine diagrams.

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Initial state of a state machine diagram is a pseudo-state from where the state machine begins its transitions. It is depicted with a black circle. Similarly, the final state is a pseudo-state where the state machine halts. The final state is shown with a circle and a filled circuit inside it.

A state machine may have another start state other than its initial state. We call this pseudo-state an entry point. Similarly, an alternative final state can be inserted into a state machine that is referred to as an exit point. An entry point is shown with a hollow circle while an exit point is shown with a circle and a cross inside it.

In some cases, there must be different paths for different conditions on an event in a state machine. A choice pseudo-state makes several decision paths in a state machine. This is shown by a diamond like that of Figure 86.36(b).

A terminate pseudo-state shows that the lifeline of the source state is finished. Therefore, it is no longer sensitive to any events. This is illustrated by a simple cross.

Another pseudo-state used in state machine diagrams is the junction pseudo-state. Junction is used to make sequences of transitions. It has multiple inputs and multiple outputs. An example of a junction pseudo-state is depicted in Figure 86.33.

A history pseudo-state in a state machine diagram stores the most recent state of a system. It is useful when an interrupt occurs in the system.

A new feature added in UML 2.0 is concurrency in state machines. In concurrent regions, the states can be executed concurrently. Their symbols are similar to fork and join nodes in activity diagrams (see Section 86.1.3.5). Figure 86.34 shows two concurrent states, CS1 and CS2.

Another element used in a state machine diagram is a transition shown in Figure 86.35. A transition is depicted with an arrow between two states. It causes the current state of the state machine to change from the source state to the target state. A transition in UML is constructed from three parts that include trigger, guard, and effect. A trigger can be an event, a signal, a value change, or a timeout. A trigger is the main reason why a transition happens. A guard is the condition that must be true when a trigger happens in a transition. An effect is an action that must happen when a trigger with a true guard occurs. The effect part of a transition is sometimes placed in the target state (in this case the effect is called a state action).

Source and destination of a transition can be identical. This transition is called a self transition. The example state transition diagram of Figure 86.36(a) and Figure 86.36(b) is part of our SSimBoard example.

Timing Diagram

Another diagram, new in UML 2.0, is the timing diagram. In this diagram, changes of a state (in a state machine) or values of an element (for example, an attribute of a class instance) are depicted over time. This diagram is very useful for hardware design. The horizontal axis of timing diagram represents the time, while the list of possible states or the names of the variables are shown on the vertical axis.

State lifeline displays the changes of a state, while value lifeline shows the value changes of an element in the diagram. Figure 86.37(a) depicts a timing diagram (state lifeline) of the state machine shown in

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Figure 86.36(a). A timing diagram (value lifeline) of the program counter attribute used in Sayeh processor is shown in Figure 86.37(b).

Our Coverage of UML

This section gave an overview of UML 2.0 diagrams. Using these diagrams, a hardware designer can develop a model from a design specification. He or she can use CASE tools to convert this model into codes in a high-level programming language. In the next section, we will discuss C/C++ high-level programming languages which can specify an early prototype of a system. This early prototype helps designers analyze their design for performance and partitioning.

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