System Level Design Languages:The Role of UML in Hardware Design

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The Role of UML in Hardware Design

In recent years, modeling a complicated software system with UML and starting software design development with CASE tools has become a standard way of software design. In other words, using a unified and standard methodology has become common in software development processes. Since there is no well-defined system level design methodology for hardware, designers have started to think about a unified hardware design methodology. Since UML is a modeling language, it can be used to model any system, not necessarily a software system. Therefore, many hardware designers see the opportunity of using UML in hardware designs as well as software. Although this language had many useful constructs and diagrams for hardware design, it lacked a few concepts that were essential in hardware design. For example, in the early versions of UML, the concurrency concept was not developed in a manner that would fit hardware descriptions. In addition, there were no diagrams to show the timing details of a system a concept which is very critical for hardware modeling. These problems made UML a difficult method of hardware description. A proposed hardware design methodology is shown in Figure 86.2.

In 2004, OMG and its contributor companies released UML version 2.0. In this version, a number of major revisions were made and new diagrams and concepts (e.g., timing diagrams and concurrency for state machine diagrams) were also added to the language. These newly added features are useful for hardware design. There are 13 diagrams in this version of UML that can be used to model different parts of a design specification. Concurrency has also been added to several of these diagrams to make it suitable for hardware designs.

There are still efforts to be made for filling the gaps between hardware design needs and UML. Recently, the Systems Modeling Language (SysML) group issued an RFP for developing a customized version of UML which is useful for systems engineering. The goal of SysML is to develop a standard language for analyzing, designing, and verifying complex systems. The draft version (version 0.9) of SysML specifica- tion was prepared in January 2005.

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