CMOS/BiCMOS Technology:BiCMOS Technology.

By -
BiCMOS Technology

Development of BiCMOS technology began in the early 1980s. In general, bipolar devices are attractive because of their high speed, better gain, better driving capability, and low wide-band noise properties that allow high-quality analog performance. CMOS is particularly attractive for digital applications because of its low power and high packing density. Thus the combination would not only lead to the replacement and improvement of existing ICs but would also provide access to completely new circuits.

Figure 2.25 shows a typical BiCMOS structure [112]. Generally, BiCMOS has vertical npn bipolar junction transistor, lateral pnp transistor, and CMOS on the same chip. Furthermore, if additional mask steps are allowed, passive devices are integrated, as described in the previous section. The main feature of the BiCMOS structure is the existence of a buried layer because bipolar processes require an epitaxial layer grown on a heavily doped n+ subcollector to reduce collector resistance.

Figure 2.26 shows typical process flow of BiCMOS. This is the simplest arrangement for incorporating bipolar devices and a kind of low-cost BiCMOS. Here, the BiCMOS process is completed with minimum additional process steps required to form the npn bipolar device, transforming the CMOS baseline process to a full BiCMOS technology. For this purpose, many processes are merged. p Tub of n-MOSFET shares an isolation of bipolar devices, n tub of p-MOSFET device is used for the collector, the n+ source and drain are used for the emitter regions and collector contacts, and also extrinsic base contacts have the p+ source and drain of PMOS device for common use.

CMOS-BiCMOS Technology-0031

CMOS-BiCMOS Technology-0032

Recently, there have been two significant uses of BiCMOS technology. One is high-performance MPU [113] by using the high driving capability of bipolar transistor, the other is mixed-signal products that utilize the excellent analog performance of bipolar transistor, as shown in Table 2.2.

For high-performance MPU, merged processes were commonly used, and the mature version of the MPU product has been replaced by CMOS LSI. However, this application is becoming less popular now with reduction in the supply voltage. Mixed-signal BiCMOS requires high performance, especially with respect to fT , fmax, and low-noise figure. Hence, double polysilicon structure with silicon [114] or SiGe [115–120] epitaxial base with trench isolation technology is used. Recently, ultra-high cutoff frequency SiGe heterojunction bipolar transistor (HBT) BiCMOS [121,122] and SiGe:C HBT BiCMOS [123–126] are reported, and design rule is shrunk to 90 nm CMOS technology [127].

Fabrication cost of BiCMOS is a serious problem, and thus a low-cost mixed-signal BiCMOS process [128] has also been proposed.

Modeling issue of BiCMOS technology is the same as that of bipolar junction transistor and CMOS devices. In the case of bipolar, the Gummel-Poon [129] model is very useful for circuit simulation, and advanced model such as VBIC [130] can also be applied.

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more