Multidimensional Logarithmic Number System:Single Sign-Bit Architecture

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Single Sign-Bit Architecture

The data path of the MDLNS processor (shown in Figure 84.1) is affected significantly by the signs of the operands. The required sign correction operation comes at a cost of additional logic and power. Thus far, our particular filter architecture requires additional processing to be performed after the MDLNS processor such as summing all the channels. It is possible to use the common single sign-bit binary representation for the intermediate results. We have therefore developed a new MDLNS sign system to reduce the processing path of the MDLNS inner product CU while producing a single sign-bit binary representation.

Our original MDLNS notation uses two bits to represent the sign for each digit (-1, 0, and 1). There are only three of four states used, one of which (zero) represents only a single value. Using two sign bits results in having nearly 50% of the representation space unused. To improve this ratio, only a single sign bit is needed to represent the most used cases (-1 and 1). We now represent zero by setting the nonbinary exponents to their most negative values (i.e., if the range is [-4, 3], then -4 is used to represent zero). This allows us to reduce the circuitry of the system while maintaining the independent processing of the exponents; this modification is easily integrated into the existing two-bit sign architecture. This special case for zero still leaves us with unused representation space, but not nearly as much as with the two sign-bit system.

By using the single sign-bit architecture for a four-channel filter, the word length for the 2DLNS representation of the coefficients and data are reduced by 2 bits. The 2DLNS processor is improved since it no longer needs to handle the negative or special zero case; only the absolute output is required. The coefficient and data signs are simply XORed to produce the output sign that is used along with the absolute output, to determine the final sum (see Figure 84.13).

In the case of a two-digit data and coefficient system, the four channels and output accumulation process is simplified with a single sign-bit by using only four adder/subtractor components and simple logic to coordinate the proper series of operations (see Figure 84.14). The processing delay from the LUTs is only three arithmetic operations and the overall logic is also reduced since the four adder/subtractor components are smaller than the four separate adder and 2’s complement generator components.

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