System Level Design Languages:SystemC

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SystemC

This section gives a brief overview of SystemC, which has now become the IEEE Std-1666 standard [6]. Although many designers consider SystemC as a language, it is a library written in C++ language. About 10 years ago, in the mid-1990s, designers and engineers from Synopsys, University of California at Irvine, Frontier Design, and IMEC introduced the SystemC idea. Then in 1999 the beta version of this library (version 0.9) was released by the OSCI organization. OCSI (Open SystemC Initiative) is an independent, not-for-profit organization that contributes to development of SystemC and other related libraries. Many EDA companies and universities are working with OSCI for developing SystemC and other system-level- related libraries.

The first version of SystemC (version 1.0) was released in 2000. This version includes implementation for data types, processes, modules, ports, etc. The classes implemented for this library have a simulation kernel, which handles events. The kernel in this version was cycle-based. In the following year, in 2001, the second version of this library was released by OSCI. This version was more stable than the previous one, and its kernel, which was event-based, was the major difference between this version and the previous version. This version became version 2.0 and was much faster than version 1.0.

After releasing version 2.0, minor revisions, changes, and bug fixings were made in version 2.0.1. Then, in 2005, OSCI released SystemC version 2.1. In this version, a few problems of the previous versions were fixed, and a few concepts (like sc_export) are added to this library for system level design. After being finalized, OSCI submitted this version of SystemC to IEEE standardization. These days, OSCI is working on the standardization of this library. In December 2005, the IEEE institute standardized the SystemC languages as the IEEE Std-1666 [6].

SystemC version 3.0 that is being planned as the next version of SystemC will focus on operating system (OS) modeling and embedded software models. Both of these features help designers in hardware/ software codesign.

The next section discusses the role of SystemC in hardware design. Then the syntax of SystemC (like its data types, module definitions, port definitions, and channel definitions) will be described followed by an example of a simple processor. The reader can refer to Refs. [6,7] for more details of SystemC syntax and constructs.

The Role of SystemC in Hardware Design

As stated above in Section 86.2, C++ can be used for system level modeling. SystemC is a C++ class library that has certain characteristics that lean more toward description of hardware. Because of these characteristics, SystemC has become a popular language for description of hardware when system level design is an issue. The main hardware-oriented parameters that cannot be seen explicitly in C++ and are implemented in SystemC are as follows:

• Time: The notion of simulation time (e.g., nanoseconds and picoseconds) has been added to this library.

Concurrency: C++ is a sequential language, which means that every statement is executed after its previous one. However, hardware components in a circuit are concurrent. Therefore, to model hardware components, we need to have a means of expressing concurrency. This implies that

different portions of the hardware model must be simulated in one simulation time. This ability has been implemented in the SystemC library using processes such as SC_THREAD and SC_METHOD.

• Hardware data types: A software programming language has its own types such as integer, fixed point, and floating point real numbers. In contrast, hardware models have their own types for their interconnection wires. For example, Z (high impedance) is not defined in C++. These hardware-specific types and their operations (like AND and OR) have been implemented in the SystemC library.

The above facilities implemented in SystemC ease the use of this library as a hardware modeling language. But there can still be questions as to why we should use SystemC as opposed to other hardware-oriented HDLs like Verilog and VHDL. The original goal of developing a library in C++ was that designers needed a unified environment for developing hardware as well as software. This common language helps designers test and debug their designs that include hardware and software simultaneously.

Another goal of developing SystemC is system level design. Designers can develop their models using SystemC in any level of abstraction. These levels include system, register transfer, and even gate level. SystemC has the necessary constructs for each of these levels. But, as the name implies, most designers prefer to use SystemC at the system level. Many designers prefer to develop their RTL or gate-level designs in the traditional HDLs with which they are most familiar. Such codes are then automatically converted into SystemC enabling cosimulation and coverification of hardware and software parts.

As stated above, SystemC is widely used in system level designs, and simulates faster when compared to traditional HDLs (like VHDL and Verilog). This is because in RTL designs the number of events is increased dramatically (compared to system level designs). Simulation speed is very important at the early stages of the design, since it can be used in analyzing the whole system for partitioning. As HDLs do not have this capability, SystemC has a great advantage for being used at the system level.

The use of SystemC by designers for high-level system design is becoming more popular. After releasing this library, other facility libraries have been released by OSCI. These libraries include

• Master-Slave library: This library contains functions and classes for abstract communications. Different levels of communication can be modeled with this library (like bus-functional and cycle- accurate). This library is useful for designs that have one or more processors with bus-based communication between these processors and other parts of the design. Since this library models different levels of abstraction for bus communication, it can also be used for interface synthesis.

• Verification library (SCV): This library contains several methods and classes for helping designers verify their SystemC designs more rapidly and easily. It facilitates developing better testbenches. This library contains methods for assertions, random number generation, etc.

Figure 86.48 illustrates the flow of using SystemC for designs.

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