VLSI Architectures for Forward Error-Control Decoders:High-Speed MAP Decoder Architectures

By -
High-Speed MAP Decoder Architectures

In this section, we present techniques for improving the throughput of recursive data-flow graph present in the MAP decoder, in particular in the ACS kernel. First, we review existing techniques of parallel processing [51,52] and look-ahead transform [36,53]. Then, we present the block-interleaved pipelining (BIP) technique [54–56].

In general, pipelining or parallel processing becomes difficult for a recursive data-path. However, if the data is being processed in blocks and the processing satisfies the following two properties: (1) computation

VLSI Architectures for Forward Error-Control Decoders-0123

between blocks are independent and (2) computation within a block is recursive, then, a block parallel processing architecture can be achieved. Further, if a block can be segmented into computationally independent subblocks, parallel processing can be applied at the subblock level. This leads to the high- throughput MAP decoder architectures presented in Refs. [51,52,54–56].

(1) Parallel Processing. Consider the recursive architecture in Figure 82.16(a). Note that the architecture in this figure cannot be easily pipelined or parallelized owing to the presence of the feedback loop. However, if a data block of length B is processed independently of other blocks and the computations within a block can be segmented into computationally independent subblocks, then one can parallelize the architecture as shown in Figure 82.16(b), where the parallelization factor M = 2 and a block X is divided into M = 2 subblocks, X1 and X2. It is obvious that the critical path is not affected and the throughput is increased by a factor of M at the expense of a factor of M increase in hardware complexity.

(2) Look-ahead transform. Another transform to achieve high-throughput for recursive data-flow graphs is look-ahead computation [53]. Look-ahead leads to an increase in the number of symbols processed at each time step as shown in Figure 82.17, where two symbols are processed in one clock cycle. If x(n) = [x(2n - 1), x(2n)] and y(n) = [y(2n - 1), y(2n)], then look-ahead results in the output being expressed as y(n) = F(x(n), y(2(n - 1)). Note that F(×) will have a longer critical path delay than the original computation of Figure 82.16(a). However, it has been shown that the function F(×) can be optimized via logic minimization so that an overall increase in throughput can be achieved. For example, as mentioned earlier, in the context of Viterbi decoding, it has been shown that a 1.7X increase in throughput is feasible via radix-4 computation [36].

(3) BIP. The parallel architecture in Figure 82.16(b), where the level of parallelism is equal to 2, has two identical computation units processing two independent input symbols. Therefore, the hardware complexity increases linearly with the level of parallelism M. A comparatively area-efficient architecture is obtained by using the BIP technique proposed in Ref. [58]. First, the data-flow of Figure 82.16(b) is folded [53] on to a single computation unit as shown in Figure 82.18(a), where two independent computations are carried out in a single computational unit. Note that the resulting BIP architecture in this figure is inherently pipelined. Therefore, an application of retiming [53] (see Figure 82.18(b)) results in reduction of the critical path delay by a factor of two over that of the original architecture in Figure 82.16(a). It is clear that the retimed BIP architecture in Figure 82.18(b) leads to high throughput at the cost of a marginal increase in memory owing to pipelining latches when compared to the architecture in Figure 82.16(a).

VLSI Architectures for Forward Error-Control Decoders-0124

Comments

Post a Comment

Popular posts from this blog

SRAM:Decoder and Word-Line Decoding Circuit [10–13].

By -
Image
Decoder and Word-Line Decoding Circuit [10–13] Two kinds of decoders are used in SRAM: the row decoder and the column decoder. Row decoders are needed to select one row of word-lines out of a set of rows in the array. A fast decoder can be implemented by using AND/NAND and OR/NOR gates. Figure 52.7 shows the schematic diagrams of static and dynamic AND gate decoders. The static NAND-type structure is chosen due to its low power consumption, that is, only the decoded row transitions. The dynamic structure is chosen due to its speed and power improvement over conventional static NAND gates. From a low-voltage operation standpoint, a dynamic NOR-base decoding would provide lower delay times through the decoder due to the limited amount of stacking of devices. Figure 52.8 shows circuit diagrams of dynamic NOR gates. The dynamic CMOS gate as shown in Figure 52.8(a) consists of input- NMOSs whose drain nodes are precharged to a high level by a PMOS when a clock signal Φ is at a low lev...
Read more

ASIC and Custom IC Cell Information Representation:GDS2

By -
Image
GDS2 The Graphical Design System (GDS) format is a binary format developed by Calma Company in 1971 to convey IC layout information between IC designers and fabricators. Calma presented GDS2 format, the improved version of GDS, in 1978. Finally in 1991, when Cadence acquired Calma, GDS2 rights were transferred to it. In the design process, after the completion of routing and placement, design rule check (DRC) and layout versus schematic (LVS) are performed to verify the final layout. Then the verified layout, dumped in a GDS2 file, is transferred to IC foundries for fabrication. GDS2 File Format GDS2 is a standard mask layout intermediate format containing a single cell or a library of cells each of which includes a number of geometrical objects such as boundaries, paths, boxes, etc. These objects correspond to different layers of a cell where each layer is specified by a layer number and data type [3]. The file format of GDS2 is in binary. A GDS2 file contains a number of variable...
Read more

Timing Description Languages:SDF

By -
Image
SDF Standard Delay Format (SDF) is an ASCII format used to convey timing information between EDA tools. SDF was first developed by Cadence in 1990. Open Verilog International (OVI) approved SDF version 2 in 1993 and SDF version 2.1 and 3 in the following years. Improving SDF version 3 features, resulted in IEEE Standard 1497 [1]. Role of SDF in Design Process SDF can be used in different levels of a design process to annotate timing specifications, including timing data and constraints. Timing constraints are used during the forward-annotation process while timing data are applied during the back-annotation process. Forward-annotation process deals with porting timing constraints to synthesis, floorplanner, layout, and routing tools to meet the required constraints. During the design process, timing data can be back-annotated to analysis tools (including simulators, static timing analysis tools, etc.) to provide more accurate timing representations. SDF Structure An SDF f...
Read more