VLSI Architectures for Forward Error-Control Decoders:Low-Power Turbo Decoder Architectures

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Low-Power Turbo Decoder Architectures

The application of BIP, folding, and retiming reduces the critical path delay in the ACS kernel of MAP decoders with marginal area overhead. Subsequent application of voltage scaling can result in savings in power keeping the same throughput. A low-power decoder architecture can be obtained by processing M subblocks of size B/M bits via subblock interleaved computations, where B denotes the block length of information bits. In this section, we present results related to achievable power savings in turbo decoders by combining voltage scaling and BIP.

To reduce power, we scale the supply voltage of the block-interleaved architecture such that the block processing time is made equal to that of the conventional architecture. The conventional architecture requires B + 2L cycles to process a block, where L is the warm-up depth. The proposed architecture requires

VLSI Architectures for Forward Error-Control Decoders-0126

where tcri,p and tcri,s are the critical path delays of the block-interleaved and conventional architectures, respectively. Thus, we can reduce the supply voltage such that tcri,p is equal to tcri,s ´ B + 2L/B + 2ML.

Figure 82.21 depicts the critical path delay ratio, area overhead ratio, and power savings for K = 3, B = 1024, and L = 16 for velocity saturation index values of a = 1 and 2. It is observed that at a certain point there is no further power savings owing to the area overhead. Further, as the number of states (=2K-1) is increased, the power savings decrease because the area overhead increases rapidly for large values of K (see Figure 82.22).

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