RT Level Hardware Description with VHDL:Design with VHDL

This chapter presents register transfer level VHDL for describing a design for performing behavioral simulation and synthesis. The purpose is to familiarize readers with the main topics of VHDL and present this language such that after reading this chapter readers can start writing VHDL code for actual designs. For this purpose, many of the complex VHDL constructs related to timing and fine modeling features of this language will not be covered here. Furthermore, we will only cover predefined standard types and not get into type definitions and complex language packages. The chapter first describes VHDL with emphasis on design using simple examples. We will cover the basics, just enough to describe our examples. In a later section, after a general familiarity with the language is gained, more complex features of this language with emphasis on testbench development will be described.

Design with VHDL

VHDL (VHSIC hardware description language) became the IEEE standard 1076 in 1987. Since then it has gone through several minor revisions, and its most common version is the IEEE 1076-1993. VHDL was an important factor in moving digital designs from the gate level to RTL.

VHDL is a rich language for having many features for description of designs from gate level to system level. However, as far as hardware design is concerned, only a small subset of this language is used. This subset includes synthesizable language constructs for description of combinational and sequential components.

For a beginner wanting to learn VHDL for design and synthesis, this chapter provides the necessary basic information. Although gate level descriptions are not often used for synthesis, to cover basic concepts of VHDL, this chapter discusses gate level design, but focuses on register transfer level. To provide designers with tools for testing circuits that they are designing, a section will be devoted to basics of testbenches in VHDL.

Entities and Architectures

Entities used in VHDL for description of hardware components are defined as a pair of entity and architecture declaration. The interface of the circuit is specified by its entity, while its operation is described by architecture bodies associated with that entity. The cause for allowing multiple architectures associated with an entity is having configurable designs for a given interface.

As shown in Figure 87.1 the interface specification of a circuit begins with the entity keyword and is followed by the name of the entity together with is. Entity declaration contains a list of the component’s input–output ports and their types. In contrast, the architecture specification begins with the architecture keyword and describes the functionality of a defined entity. The functionality of the component is described using gate instantiations, signal assignments, and processes in the architecture body. The architecture body consists of two parts: the declarative part and the statement part. The declarative part is the section before the begin keyword, while the statement part is enclosed between begin and end of the architecture. The repeat of architecture or entity names after the end keyword is optional in both entity and architecture specifications.

A design may be described in a hierarchy of entities, which means that a module can be composed of several submodules. Component instantiation is the construct used for bringing a lower level entity into a higher level one. The connections between these submodules are defined within the architecture of the top-level module. Figure 87.2 shows a hierarchy of components.

The operation of an entity can be described in several ways. Architecture simple1 in Figure 87.3 describes a circuit in the gate level. This is done by a component instantiation. Architecture simple2 shows a signal assignment, while architecture simple3 uses a process statement to describe the functionality of the design. A process is used for behavioral descriptions of the design. A process is recognized with the process keyword and includes sequential statements. The execution of a process is triggered by events. These events are either listed in a sensitivity list enclosed in a set of parenthesis or wait statements are used to control the process execution. However, we will be using the former throughout this chapter.

Entity Ports and Signals

Following the port keyword in an entity declaration is a set of parenthesis with a list of input–output ports. A port may be declared as in, out, inout, or buffer. In and out modes are used for declaring

input and output ports, respectively. The inout mode is mainly used for bidirectional lines, which implies both an input side and an output side. On the other hand, buffer is primarily used for output ports, which are read in the same body as they are driven.

As shown in Figure 87.4, each port also requires a type specification. Type bit is a predefined VHDL type which has been used in this example. We will be using this type for now but keep in mind that other standard and user-defined types are also allowed.

In addition to ports, signals can be declared as data carriers in an architecture. Signal declaration takes place in the declarative part of an architecture between the architecture header and the begin keyword. Similar to signals, variables are used as intermediate carriers with the difference of only being accessible in process bodies. Therefore in addition to ports, signals are the only data objects that can carry data between processes and other concurrent components.

The std_logic standard package defines a logic value system consisting of nine logic values. However, std_logic is not a part of the VHDL language and is only an IEEE standard utility package for the language. The nine values of std_logic, which are shown in Table 87.1, are used to represent high impedance, unknown, unini- tialized, capacitive, and resistive 1 or 0, and driven 1 or 0. In most cases only four or five of these nine [2] values are sufficient to express the logic-level behavior of a circuit. U is considered as the default type.

Since the std_logic type includes all values of the bit type, we will be using it instead of bit type from now onward in the chapter. The std_logic_unsigned package, which will be used for unsigned types, contains a set of signed arithmetic, conversion, and comparison functions. Finally, it should be kept in mind that special care needs to be taken as VHDL has very strict type checking rules.