Performance Modeling and Analysis Using VHDL and System:A Three Computer System.

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A Three Computer System

This section discusses a simple example to illustrate how the modules discussed previously may be interconnected to model and evaluate the performance of a complete system. The system to be modeled consists of three computers communicating over a common bus, as shown in Figure 77.12. Each block representing a computer can be thought to contain its own processor, memory and peripheral devices. The actual ADEPT schematic for the three computer system is shown in Figure 77.13.

Computer C1 contains some sensors and preprocessing capabilities. It collects data from the environment, converts it into a more compact form and then sends it to computer C2 via the bus. The computer C2 further processes the data and passes it to computer C3 where the data are appropriately utilized. It is assumed that data are transferred in packets and each packet of data are of varying length. In the example described here, computers C1 and C2 receive packets whose sizes are uniformly distributed between 0 and 100. The packet

Performance Modeling and Analysis Using VHDL and SystemC-0074

size of computer C3 is uniformly distributed between 0 and 500. The external environment in this example is modeled by a Source module in C1 and a Sink module in C3.

C1 has an output queue, C2 has both an input queue and an output queue, while C3 has one input queue. All queues in this example are assumed to be of length 8. If the input queues of C2 or C3 are full the corresponding Q_free signal is released (value=RELEASED). This interconnection prevents the computer writing into the corresponding queue from placing data on the bus when the queue is full. This technique not only prevents the bus from being unnecessarily held up but also eliminates the possibility of a deadlock.

The ADEPT model of Computer 1 (C1) is shown in Figure 77.14. The Source A (SOA) module along with the Sequence A (SA), Set_Color A (SCA), and Random A (RA) modules generates tokens whose tag1 field is set according to a distribution which is representative of the varying data sizes that C1 receives. The Data-Dependent Delay A (DDA) models the processing time of C1 which is directly proportional to the packet size. The unit_step delay for the DDA module is passed down as a generic d1*1 ns. As soon

Performance Modeling and Analysis Using VHDL and SystemC-0075

as a token, representing one packet of data, appears at the output of the DDA module, the Sequence B (SB), Set_Color B (SCB), and Random B (RB) modules together set the tag1 field of the token to represent the packet size after processing. The Constant A (COA) and Set_Color C (SCC) modules set the tag2 field of the token to 2. This coloring indicates to the bus arbitration unit that the token is to be transferred to C2. The token is then placed in the output Queue (Q1) of C1 and the token is acknowledged. This acknowledge signal is passed back to the Source A module which then produces the next token. The Fixed Delay (FDA & FDB) modules represent the read and write times associated with the Queue. The Switch A (SWA) element is controlled by the Q_free signal from C2 and prevents a token from the output queue of C1 from being placed on the bus if the incoming Q_free signal is inactive.

Figure 77.15 shows the ADEPT model of Computer 2 (C2). When a token arrives at the data input of C2 the token is placed at the input of the Queue (Q2). The control output of the Queue becomes the Q2_Free output of C2. The remaining modules perform the same function as in C1 except that the tag2 field of the tokens output by C2 is set to 3 which indicates to the bus arbitration unit that the token is

Performance Modeling and Analysis Using VHDL and SystemC-0076

to be sent to C3. The DDA module represents the relative processing speed of Computer C2. The unit_step delay for the DDA module is passed down as a generic d2*1 ns.

The modules defining Computer 3 (C3) are shown in Figure 77.16. A token arriving at the input is placed in the queue. The DDA element reads one token at a time and provides the delay associated with the processing time of C3 before the Sink A (SIA) module removes the token. The unit_step delay for the DDA module is passed down as a generic d3*1 ns.

The bus is shown in Figure 77.17. Arbitration is provided to ensure that both C1 and C2 do not write onto the bus at the same time. The Arbiter A (AA) element provides the required arbitration. Since the output of C2 is connected to the IN_1(1) input of the AA element, it has a higher priority over C1. The Union A (UA) element passes a token present at either of its inputs to its output. The output of the UA element is connected to the Data-Dependent Delay A (DDA) element, which models the packet transfer delay associated with moving packets over the bus. The delay through the bus is dependent on the size of the packet of information being transferred (size stored on the tag1 field). Note that in this analysis, the bus delay was set to 0. The independent output of the Read_Color A(RCA) element is connected to

Performance Modeling and Analysis Using VHDL and SystemC-0077

the control input of the Decider A (DA) module. The base of the DA element is set to 2. Since the tag2 field of the token is set to 2 or 3 depending on whether it originated from C1 or C2, the first output of the Decider A module is connected to C2 and the second output is connected to C3. This technique ensures that the tokens are passed on to the correct destination, C2 or C3.

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