Performance Modeling and Analysis Using VHDL and System:SystemC Background

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SystemC Background

This section describes some of the basic concepts of SystemC and how it is used to model systems at a high level. SystemC is a library extension to C++. Essentially, SystemC uses a set of classes and predefined functions to build a new “language” on top of C++. The basic unit of a SystemC model is the SC_MODULE class. The SC_MODULE is roughly equivalent to an entity in VHDL. It can have input, output, and bidirectional ports. However, it is a C++ class and as such it can, and does, have member functions. Any member function that is declared as public can be accessed just like the member function of any other class. Every SC_MODULE must have at least one public member function, its constructor. In the constructor the module is given a SystemC name, and declares if it has any processes, and does anything else necessary to get the model ready for simulation. There are two types of processes in SystemC, the SC_THREAD and the SC_METHOD. The behavior of a process must first be declared as a

Performance Modeling and Analysis Using VHDL and SystemC-0095

member function, then that member function can be declared to be either an SC_THREAD or an SC_METHOD in the constructor. The primary differences are how they behave when they reach the end of their definition, and when the scheduler activates them.

An SC_THREAD will terminate, and never be activated again, if it reaches the end of its description. Typically SC_THREADs are infinite loops with one or more wait statements to break the execution, and wait on some signal change or other event. An SC_METHOD will be activated any time something it is sensitive to changes, and will run once through to the end of its description. If something an SC_METHOD is sensitive to changes again, it will run again. SC_THREADs do have the ability to use a form of the wait command that is not available to SC_METHODs. They may use a wait command with no parameters which will cause them to be reactivated and continue execution with the line after the wait statement when something in their sensitivity list has an event.

As indicated by the discussion of processes, SystemC uses an event-driven simulation methodology. The library provides basic signal classes that have a notify-update sequence much like VHDL. As mentioned in the Transaction Level Modeling discussion above, SystemC has a concept of channels. A channel is generally

Performance Modeling and Analysis Using VHDL and SystemC-0096

some means of moving information. The basic signal classes provided are base channels. A designer could potentially design some new base channel type that has the same interfaces as the existing base channels. However, building a new base channel is rather involved since its implementation must interact directly with the scheduler to implement the notify/update semantics of a signal. Additionally, such a user-designed  base channel would still only have a basic interface, and could not have any internal processes, thus would not provide significant abstraction leveraging for the amount of time required to design it. Instead designers should use what is called a hierarchical channel for most modelling needs. A hierarchical channel is a channel that is made up of a number of elements of base classes. A hierarchical channel can have any number of ports, or methods. The methods that a module could use to access the channel, and convey information through it, are called interface methods. For a module to be able to access an interface method the channel needs to have a defined interface that it inherits. The sc_interface class is used as a base class to define such an interface. The file in Figure 40 shows one such interface class. Once an interface class has been defined and inherited by the channel, then any module with a port of that type can be bound to the channel’s interface. In addition to the base channel classes, the SystemC library provides an event object that can be waited upon using the same syntax as a wait for a signal change event. For more details on the syntax, classes, and functions of SystemC the reader may refer to Ref. [12].

At the time of this writing, there are several options for simulating SystemC models. The two most robust SystemC simulators are the reference simulator, available with the SystemC distribution, and the ModelSim simulator as mentioned above. Because of some internal implementation details which differ between the two simulators, there are minor code differences required in the performance models between the two simulators. The differences and the techniques for enabling the models to be compiled and run in either simulators are described in the sections below.

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