Nyquist-Rate ADC and DAC:DAC Architectures

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DAC Architectures

An N-bit DAC provides a discrete analog output level, either voltage or current, for every level of 2N digital words that is applied to the input. Therefore, an ideal voltage DAC generates 2N discrete analog output voltages for digital inputs varying from 000…00 to 111…11. In the unipolar case, the reference point is 0 when the digital input is 000…00; but in bipolar or differential DACs, the reference point is the midpoint of the full scale when the digital input is 100…00. Although purely current-output DACs are possible, voltage-output DACs are common in most applications.

Resistor-String DAC

The simplest voltage divider is a resistor string. Reference levels can be generated by connecting 2N identical resistors in series between Vref and ground. Switches to connect the divided reference voltages to the output can be either 1-out-of-2N decoder or binary tree decoder as shown in Figure 58.28 for the 3-b example. Since it requires a good switch, the stand-alone resistor-string DAC is easier to implement using CMOS. However, the lack of switches does not limit the application of the resistor string as a voltage reference divider subblock for ADCs in other process technologies.

Resistor strings are widely used as an integral part of the flash ADC as a reference divider. All resistor- string DACs are inherently monotonic and exhibit good differential linearity. However, they suffer from poor integral linearity and also have the drawback that the output resistance depends on the digital input code. This causes a code-dependent settling time when charging the capacitive load. This non-uniform settling time problem can be alleviated by adding low-resistance parallel resistors or by compensating the MOS switch overdrive voltages.

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Current-Ratioed DAC

The most popular stand-alone DACs in use today are current-ratioed DACs. There are two types: one is a weighted-current DAC and the other is an R-2R DAC. The weighted-current DAC shown in Figure 58.29 is made of an array of switched binary-weighted current sources and the current summing network. In bipolar technology, the binary weighting is achieved by ratioed transistors and emitter resistors with binary related values of R, R/2, R/4, etc., while in MOS technology, only ratioed transistors are used. DACs relying on active device matching can achieve an 8b-level performance with a 0.2 to 0.5% matching accuracy using a 10- to 20-µm device feature size, while degeneration with thin-film resistors gives a 10b-level performance. The current sources are switched on or off by means of switching diodes or emitter-coupled differential pairs (source-coupled pairs in CMOS). The output current summing is done by a wideband transresistance amplifier; but in high-speed DACs, the output current directly drives a resistor load for maximum speed. The weighted-current design has the advantage of simplicity and high speed, but it is difficult to implement a high-resolution DAC because a wide range of emitter resistors and transistor sizes are used, and very large resistors cause problems with both temperature stability and speed.

R-2R Ladder DAC

This large resistor ratio problem is alleviated by using a resistor divider known as an R-2R ladder, as shown in Figure 58.30. The R-2R network consists of series resistors of value R and shunt resistors of value 2R. The top of each shunt resistor of value 2R has a single-pole double-throw electronic switch

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that connects the resistor either to ground or to the current summing node. The operation of the R-2R ladder network is based on the binary division of current as it flows down the ladder. At any junction of series resistor of value R, the resistance looking to the right side is 2R. Therefore, the input resistance at any junction is R, and the current splits into two equal parts at the junction since it sees equal resistances in both directions. As a result, binary-weighted currents flow into shunt resistors in the ladder. The digitally controlled switches direct the currents to either ground or to the summing node. The advantage of the R-2R ladder method is that only two values of resistors are used, greatly simplifying the task of matching or trimming and temperature tracking. In addition, for high-speed applications, relatively low resistor values can be used. Excellent results can be obtained using laser-trimmed thin-film resistor networks. Since the output of the R-2R DAC is the product of the reference voltage and the digital input word, the R-2R ladder DAC is often called an MDAC.

Capacitor-Array DAC

Capacitors made of double-poly or metal–metal in MOS technology are considered one of the most accurate passive components comparable to thin-film resistors in the bipolar process, both in the matching accuracy and voltage and temperature coefficients [1]. The only disadvantage in the capacitor- array DAC implementation is the use of a dynamic charge redistribution principle. A switched- capacitor counterpart of the resistor-string DAC is a parallel capacitor array of 2N unit capacitors with a common top plate. The capacitor-array DAC is not appropriate for stand-alone applications without a feedback amplifier virtually grounding the top plate and an output S/H or deglitcher. The operation of the capacitor-array DAC shown in Figure 58.31(a) is based on the thermometer-coded DAC principle and has the distinct advantage of monotonicity. However, due to the complexity of

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handling the thermometercoded capacitor array, a binary-weighted capacitor array is often used, as shown in Figure 58.31(b) by grouping unit capacitors in binary ratio values. One important appli- cation of the capacitor-array DAC is as a reference DAC for ADCs. As in the case of the R-2R MDAC, the capacitor-array DAC can be used as an MDAC to amplify residue voltages for multi-step or pipeline ADCs.

Thermometer-Coded Segmented DAC

Applying a two-step conversion concept, a DAC can be made in two levels using coarse and fine DACs. The fine DAC divides one coarse MSB segment into fine LSBs. If one fixed MSB segment is subdivided to generate LSBs, matching among MSB segments creates a non-monotonicity problem. However, if the next MSB segment is subdivided instead of the fixed segment, the segmented DAC can maintain mono- tonicity regardless of the MSB matching. This is called the next-segment approach. The most widely used segmented DAC is a current-ratioed DAC, whose MSB DAC is made of identical elements for the next-segment approach, except that the LSB DAC is a current divider as shown in Figure 58.32. To implement a segmented DAC using two resistor-string DACs, voltage buffers are needed to drive the LSB DAC without loading the MSB DAC. Although the resistor-string MSB DAC is monotonic, overall monotonicity is not guaranteed due to the offsets of the voltage buffers. The use of a capacitor-array LSB DAC eliminates the need for voltage buffers.

Integrator-Type DAC

As mentioned, monotonicity is guaranteed only in a thermometer-coded DAC. The thermometer coding of a DAC output can be implemented either by repeating identical DAC elements many times or by using the same element over and over. The former requires more hardware, but the latter requires more time. In the continuous-time integrator-type DAC, the integrator output is a linear ramp and the time to stop integration can be controlled digitally. Therefore, monotonicity can be maintained. Similarly, the discrete-time integrator can integrate a constant amount of charge repeatedly and the number of integrations can be controlled digitally. The integration approach can give high accuracy, but its disadvantage is that its slow speed limits its applications.

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