Low-Power Memory Circuits:Magnetic Memory

Magnetic Memory

Magnetic memories (MRAMs) offer a unique combination of performance, high density, low-power, nonvolatility, and write endurance [32–39]. There are several low-power techniques targeting write current [32,38], memory cell design [32–35], and sense amplification [36,37]. Hung et al. [32] introduced a pillar write wordline structure (PWWL) within each MRAM cell. This structure enhances magnetic field by a surrounding current path. Using this structure, the writing current can be reduced by a factor of 2. Hung et al. [32] also introduced a new memory cell comprising of one transistor and two uneven magnetic tunnel junctions (1T2UMTJ). The implementation is shown in Figure 57.20. By electrically combining two memory bits in parallel that share one transistor, one transistor can be eliminated. Two

uneven magnetic tunnel junctions (MTJs) (R1 and R2) have different magnetoresistance (MR) charac- teristics in R–I loop. They are connected to generate four distinct memory states.

Durlam et al. [34] developed the first 1 Mbit MRAM based on a one-transistor one-magnetic tunnel junction (1T1MTJ) bit cell. The cell architecture is based on the minimum-sized active transistor as the isolation device in conjunction with an MTJ. The MTJ has one electrode connected to the drain of a

pass transistor for isolation and the electrode connected to the BL (see Figure 57.21). The neighboring cells share the pass transistor source and isolation region to minimize the cell area. The total cell area is 9F2, where F is one half the metal pitch. The MRAM bit cell is programmed by the magnetic field, which is generated by a current flowing through two conductors. The transistor is turned off during this time. The direction of a BL current determines the direction of the polarization of the free layer. A special cladding layer is used to reduce the required current by a factor of 2. The group designed first 1-Mbyte MRAM with 50 ns access time consuming 24 mW in 0.6 µm CMOS process at 3.0 V power supply voltage. Asao et al. [35] developed a new cross point cell with hierarchical BL architecture. This new design, shown in Figure 57.22, increases the cell density to 6F2 and reduces the sneak current that degrades the write signal. The required read current is also small. However, the performance is reduced. The group fabricated 1-Mbit MRAM in 0.13 µm CMOS running at 1.5 V.

Aoki et al. [36] proposed a new scalable MRAM cell built with one transistor and two MTJs. This new cell is capable of sensing voltage directly divided with resistance ratio of 2MTJs (Figure 57.23). The scheme uses a folded BL architecture with fixed reference voltage that creates a large sensing margin and thus leads into a stable operation.

Two MTJs are connected in series and the connection node is joined with a BL through a pass transistor. The MTJs are identical in size and are connected with WWL1 and WWL2. During write opera- tion, a write current is applied to the DL and to both the WWL1 and the WWL2. They form a current loop. During the read, the voltage Vread is applied to MTJs. The voltage of the connection node is either

more than Vread /2 when the resistance of MTJ1 is less than MTJ2, or less than Vread /2 when the resistance of MTJ1 is more than MTJ2. Two adjacent cells share a BL contact. The cell area is 8F2. Au et al. [37] introduced a new low power-sensing scheme for MTJ MRAM (Figure 57.24). Op-amps A1s are used to generate currents Imtj and Iave. The op-amps are two-stage Miller-compensated differential amplifiers (gain 70 dB and unity gain at 150 MHz). The output resistance of the opamps is comparable to MR. M1s are current buffers necessary to drive the resistances. To improve the accuracy, the simple current mirrors can be replaced by cascode current mirrors. This sensor can operate at very low-power supply voltages; however, its sensitivity is limited to an MR ratio of 10%. By using the low-power current sense amplifier, the power consumption is reduced 1.46–3.33 times.

Last, Jeong et al. [33] introduced a novel reference cell-sensing scheme for 1T1MTJ cell structures that increases the sensing signal. This allows an increase in MR ratio which is necessary for a reliable MRAM operation. A diagram of the new sensing scheme is presented in Figure 57.25. As shown, the reference

cell is built with a pair of memory cells connected in parallel and an additional BL clamping circuit. The clamping circuit draws half of the current flowing into the reference cell. The BL and the BL bar voltages are clamped at 0.4 V. This maintains high MR ratio during sensing operation. Memory is selected by the asserted address and by column decoder lines. The differential sense amplifier compares the currents flowing into the BLs. Half of the reference cell current flows into the sense amplifier and

the other half into the additional clamping circuit. The memory was implemented in 0.24 µm CMOS technology, operated at 2 V, and an MR ratio of >30% was achieved.