High-Speed Circuit Design Principles

The digital and analog circuits used with high-speed compound semiconductor devices must satisfy the same essential conditions for design robustness and performance as integrated circuits (ICs) fabricated in other technologies. For example, the static or DC design of a logic cell must guarantee adequate voltage and current gain to restore the signal levels in a chain of similar cells. A minimum noise margin must be provided for tolerance against process variation, temperature, and induced noise from ground bounce, cross talk, and EMI so that functional circuits and systems are produced with good electrical yield. Techniques for static logic design have been clearly described in other references [1] and are basically the same for compound semiconductor IC technologies. The major difference, and this includes CMOS and SiGe BJT designs as well, occurs when speed and bandwidth are of primary concern. In that situation, propagation delays, rise and fall times, maximum clock frequencies of digital circuits, and bandwidth and transient response of analog circuits must be determined as a function of extrinsic loading and power dissipation. Compound semiconductor designs emphasize speed, so logic voltage swings are generally low—low tr so that transconductances and fT are high, and device access resistances are made as low as possible to minimize the lifetime time constant t. This combination makes circuit performance very sensitive to parasitic R, L, and C, especially when the highest operation frequency is desired. The following sections will describe some of the techniques that can be used for estimating the high- frequency performance of digital and wideband analog ICs.

The most effective methods for guiding the design are those providing insight that helps to identify the dominant time constants, which determine circuit performance. These are not necessarily the most accurate methods, but are highly useful because they allow the designer to determine what part of the circuit or device is limiting the speed. Circuit simulators are far more accurate (at least to the extent that the device models are valid), but do not provide much insight into performance limitations. Without simple analytical techniques to guide the design, performance optimization becomes a trial-and-error exercise with no guarantee of finding an optimal solution. The following sections will describe some of these techniques with particular emphasis on the devices that provide insight and can be used for estimating the high-frequency performance of logic and wideband analog ICs. It is assumed that layout parasitics will be estimated as well as part of the design process and included in the analysis. Because these are highly process-and application-dependent, they will not be considered as part of the design examples presented in the later sections.