CAD DFT and Test rchitectures:Test Architectures for System-Level DFT

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Test Architectures for System-Level DFT
Boundary Scan Standard

Digital logic modules are typically made parts of bigger systems by being mounted (packaged as chips) on printed circuit board (PCB) or by being integrated (as “bare die”) in multichip modules (MCMs). The resulting systems present their own difficulties for testing even if all participating modules have been tested prior to assembly. The main problems are faults on module interconnects and faults in the system-level behavior of the individual modules (such as insufficient driving capability). In addition, it is desirable to easily test each module under a lifetime testing policy, and also to easily isolate any faulty module(s).

To accomplish these goals, the boundary scan technique (standardized as IEEE JTAG [Joint Test Action Group] standard 1149.1) is widely used (see, e.g., Refs. [1–3]. Boundary scan requires (1) the presence of a test bus on the system, and (2) the incorporation of a small control circuitry in each of the constituent modules, with the circuitry being of course standardized for interoperability.

System-Wide Test Bus

The system-wide test bus consists of the following lines: (1) at least one test data input (TDI) and at least one test data output (TDO) line; (2) at least one test mode select (TMS) line; (3) the test clock (TCK); and (4) a test reset (TRST) line.

Each TDI and TDO pair of lines provides a serial interface to supply test data and instructions to and receive response data from the modules. All the modules may be connected serially through one TDI and one TDO line, or groups of modules may have their own TDI and TDO lines. TCK is the clock for testing purposes. This is distinct from any individual module clock and provides a common reference for testing purposes. TMS is a line that at each clock cycle provides a value to control the testing of an individual module. TRST is an optional line that can be used to reset the test logic of the modules.

Module Control Circuitry

A boundary scan-compliant module must incorporate the following logic (Figure 68.5): (1) a boundary scan chain; (2) a test access port (TAP); (3) a TAP controller; (4) an instruction register; (5) a 1-bit bypass register; and (6) a device identification register plus other optional registers.

The boundary scan chain consists of individual boundary scan cells, one cell for each input and each output pin of the module. The structure of a boundary scan cell is shown in Figure 68.6. The double flip-flop configuration (one flip-flop controlled by Clock_DR and the other by Update_DR) ensures that the values on the inputs and outputs of the module logic are not affected, while test values are being shifted through the boundary scan chain. The boundary scan cells can provide (in test mode) test values to the module’s input pins and capture the responses from the output pins. This is done in a serial manner through the shifting operation of the boundary scan chain and eventually through the TDI and TDO lines of the system test bus.

The TAP consists of the pins necessary to interface with the system–wide test bus, namely: TDI, TDO, TCK, TMS, and (optionally) TRST. The TDI and TDO pins of the module are used to control/observe serially the value of any register in the circuitry, namely, the boundary scan chain, instruction register, bypass register, device identification register, as well as any internal scan chains of the module. The TAP controller is a small synchronous finite state machine with 16 states. The state transitions are determined by the value that the TMS signal has at each clock cycle. Each state generates appropriate output signals to control the function of the instruction register, the boundary scan chain, and any required test data register.

CAD DFT and Test Architectures-0302

The instruction register holds the test instruction (serially supplied through the TDI pin) which each time controls the operation of the module’s test logic. The mandatory test instructions are BYPASS, SAMPLE/ PRELOAD, and EXTEST. The BYPASS instruction connects the bypass register alone between the module’s TDI and TDO pins without the intervention of the boundary scan chain. This is very useful in reducing the length of the system–wide boundary scan chain and thus delivers faster the test data to and from the module under test. The SAMPLE/PRELOAD instruction allows the transfer of the module I/O pin values to the boundary scan cells without disrupting normal operation. It also allows preloading of the boundary scan chain by shifting in values to the flip-flops controlled by Clock_DR (Figure 68.6). The EXTEST instruction is used to test the logic around the module, primarily the system interconnects. The system values coming into the module’s inputs are captured by the input boundary scan cells and the system lines normally driven by the module’s outputs are driven by the output boundary scan cells. There are additional test instructions that can be optionally used such as the INTEST and RUNBIST, which are used to test the logic of the module as a stand-alone entity.

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