CAD DFT and Test rchitectures:Circuit-Level DFTand Scan Designs

Design for testability (DFT) constitutes a set of design rules that must be followed in the design phase to improve the testability of faults that model physical defects. They are further distinguished among techniques that are applied at the circuit level or at the system level and are discussed in Sections 68.1 and 68.2 below.

Circuit-Level DFT: Scan Designs

Circuit-level DFT is either empirical or automated [1,2]. The former consists of a list of practices that have been applied successfully in testing. Following such empirical rules, circuits are designed so that each embedded flip-flop must be initializable, a gate should not have large number of fan-ins because the inputs are difficult to control and the output is difficult to observe, direct control during testing must be provided for embedded signals that are difficult to control. Unless such methods are supplemented by automated methods, such empirical methods do not perform well on test that are provided by automatic test pattern generation (ATPG) tools. In most cases, they require manual test generation which is impractical in VLSI.

In automated DFT methods circuitry is added to allow testing under a predetermined manner. They are further distinguishable as built-in self-test (BIST) methods and scan-based methods. BIST is examined in a later chapter because it involves elaborate methods to automate the design of circuitry that generates the test patterns and analyzes the circuit responses. This section studies the principle of scan where an extra mode, referred to as the test mode, allows the flip-flops to form one or more registers, referred to as the scan registers. This is the conventional scan method. It has been suggested that this operation can be virtually performed as a Random Access Memory in which case the approach is referred to as random access scan. Both the conventional and random access scan are distinguished as full scan where all flip-flops participate in the test function or partial scan where only a subset of flip-flops participate.

A popular method to select a subset of flip-flops for scan is the structural partial scan method. In this approach, the structure graph of the sequential circuit is constructed [2]. In this graph the very node corresponds to a flip-flop, and a directed edge from node a to node b indicates that there is a directed path from flip-flop a to flip-flop b that consists of combinational components. Then nodes are removed from this graph, and the respective flip-flops are scanned. A minimum number of nodes must be removed so that the structure graph becomes acyclic (self-loops need not be eliminated), and then the longest path in the acyclic graph is less than a predefined bound. The latter quantity is also referred to as the sequential depth, and determines an upper bound on the sequence of patterns that must be applied to detect faults that model physical defects. The smaller the sequential depth, the smaller is the length of the sequence.

In scan-based designs only D-type master–slave flip-flops should be used, as in Figure 68.1. At least one primary input pin must be available for test. If more than one pins is available, then multiple scan registers are formed. It is also important that all clock signals are controllable from primary inputs and that they should not feed data inputs of flip-flops. If the latter is not followed, then races may occur in the operational mode of the circuit.

Figure 68.2 shows a scan flip-flop design with only clock signal (CK). When the test control signal (T) is 1, the input data (D) are stored in the flip-flop; when T is 0, the shift data (S) are stored.

Figure 68.3 shows the level-sensitive scan design (LSSD) flip-flop where there are two nonoverlapping clock signals, the master clock (M_CK) and the slave clock (S_CK). When M_CK is 1, D is stored in the master latch and when S_CK is high, D is stored in the slave latch. They are never both set to 1. To operate in scan mode, M_CK is set to 0 and then data S are stored using T and S_CK as master and slave clocks, respectively [1,2]. This design reduces the performance degradation owing to the added multiplexer required to implement the scan mode.

Testing of circuits with scan is done in two phases. First, a toggle sequence is shifted into the scan register to test for defects in the shift register that may impact its correctness as far as the shift operation is concerned. The sequence must produce the two transitions and 2-bit stable value subsequences in each flip-flop. Its length is the number of scanned flip-flops plus four.

In the second phase, faults in the combinational logic are targeted. Assume that the test set consists of a collection of test patterns that must be applied to the combinational logic. Each pattern consists of the input portion (bit values that must be applied to the primary inputs) and the scan portion (bit values that must be stored into the scan flip-flops). Each pattern is applied in the operational mode, but prior to that the test mode is used to shift-in the scan portion. This requires, in the worst case, as many clocks as the number of flip-flops in the scan register. Once the pattern is applied, using a single operational clock, the next pattern is shifted-in, while the latched values of the previously applied pattern are scanned-out.

When testing for delay defects, the test set collection consists of test patterns that must be applied in pairs. Figure 68.4 shows an enhancement of the scan flip-flop, called enhanced scan flip-flop, where an additional latch allows for any pair of input vectors to be applied to the combinational logic. A pair of patterns is applied with the following sequence of operations:

First H=T= 0, and, using CK, the scan portion of the first pattern is scanned-in. Then H = T = 1, and the input portion of the first pattern is applied. Then the above procedure is repeated for the second pattern. Then H = 0 and CK is applied to capture the output of the combinational logic that drives the scan flip-flops. Then T = 0 and the contents of the flip-flops are scanned-out.