Automatic Test Pattern Generation:Delay Faults.

Delay Faults

Defects may cause the propagation time along paths in the CUT to exceed the dock period. Such types of faults are called delay faults. Several fault models have been proposed to detect delay faults. Independent of the model used, a test for a fault requires that transition must be propagated from the fault site to an observable point. Therefore more than one test pattern must be applied to detect a delay fault. A pair of patterns is required if the CUT is combinational. The pattern pair must also generate a transition in at least one input of the CUT.

In sequential logic, an enhanced scan design is required so that any pair of test patterns can be applied to the CUT. This DFT approach is discussed in the previous chapter. If traditional scan is used, then the ATPG process must be modified so that the second pattern in the pair is obtained from the first one. Two methods have been proposed, the broad-side delay test and the scan-shift delay test [3].

In the broad-side test, the flip-flop portion of the second pattern must be obtained when applying the first pattern. The first pattern is scanned-in and then the application of the primary input bits produces the flip-flop portion of the second pattern. Then an application of the clock in the normal mode and the application of the primary input portion of the second pattern brings a transition generated at some inputs of the embedded combinational core. The CUT is kept in normal mode, and the outputs are observed or scanned-out after one rated-clock period.

In scan-shift test, the second pattern is generated by scanning the first pattern by one bit. The scan-in of the first pattern is followed by a slow-clock cycle while the CUT remains in scan mode. When the second pattern is applied the mode changes from scan to normal, and the outputs are latched with one application of a rated clock. They are directly observed or scanned-out as in the previous approach.

The first pattern can be applied with a slow clock so that the logic values on all lines settle to their final value before the second pattern is applied. This method, also called slow-fast clock application requires that the Automatic Test Equipment (ATE) has two test clocks. Alternatively, both patterns can be applied with the rated-clock. This is called at-speed testing. Although at-speed tests require less expensive ATE, they do not cover as many faults as the variable clock-tests.

If the sequential logic does not have full-scan support, then more than two patterns must be applied. All of them can be applied at the rated speed (at-speed nonscan sequential test) or some of them can be applied at a slow clock and the other at the rated-speed (variable clock nonscan sequential test).

The remaining of this section assumes that the CUT is combinational or that enhanced scan is provided. In addition, it is assumed that the first pattern is applied using a slow clock and the second using a rated clock.

A suitable fault model to detect gross delay defects is the transition fault (TF) model. There exist two possible faults per line, a slow-rising and a slow-falling transition. Thus, the total number of TF faults is twice as many as the number of lines in the CUT. This number is the same as the number of SSFs. A test for a single stuck-at 0 on that line can be used effectively when generating a pair of test patterns to detect a slow-rising TF. This test sets the line to 1 in the fault-free circuit, and propagates an error to an output or, equivalently, ensures that any change at the fault site is observable to an output. This test will be used as the second test pattern in the pair. The first pattern must set the line to 0. Similarly, one can derive a pair of test patterns for detecting a slow-falling TF so that the first pattern sets the line to 0 and second pattern is a test for a single stuck-at 1 on that line.

Similar to the ATPG process, fault grading techniques for SSFs can be modified to apply for TFs. The fundamental assumption for TF tests is that hazards do not interfere with the observation of the propagation of the delayed transition from the fault site to the output. The delay defect must also be large enough so that it is detected even if it propagates along short paths. This fault model is not appropriate for detecting distributed delay defects, where many small delay defects in several gates and interconnects may cause failures along a long enough path. For this reason, a more refined fault model has been proposed for delay fault testing. In this model, faults are associated with paths instead of lines, and for this reason is it called the path delay fault (PDF) model.

The following assume a fully scanned sequential circuit with enhanced scan where path delays are examined in the embedded combinational logic. A PDF is a path where a rising or a falling transition propagates along every line on it. In practice, only long enough paths, referred to as critical PDFs, are examined. However, in many circuits the majority of PDFs are long enough to be categorized as critical, and for simplicity the following assume that all the PDFs are critical. Therefore, for every physical path in the circuit, there exist two PDFs. The first PDF is associated with a rising transition on the first line on the path. The second PDF is associated with a falling transition on the first line on the path.

The fundamental difficulty of the PDF model is that the number of faults may be, and often is, exponential to the size of the CUT. For this reason both fault coverage and ATPG must be done implicitly, i.e., in a fault nonenumerative manner. In ATPG the goal is to generate a set of pairs of test patterns so that the number of tested PDFs is high. Note that the PDF model assumes that all patterns that test a PDF bring the same propagation delay along the PDF. In fault coverage, the goal is to determine how many PDFs are tested (simulated) by a given set of pairs of patterns. An ATPG or a fault coverage algorithm cannot determine the number the tested PDFs unless the tested PDFs are kept implicitly using appropriate data structures. In this case, it can be determined in polynomial time whether a particular PDF is tested or not. Unfortunately, implicit (nonenumerative) fault coverage (and therefore ATPG) is not easy. The implicit PDF coverage problem has been shown to be intractable.

There exist different ways under which a PDF can be sensitized, i.e., the transition propagate through- out the path, by a pair of test patterns. The most appropriate PDF sensitization condition is the robust condition. Robust tests guarantee detection of the PDF independent of any delays in the rest of the circuit. This is the most desirable way of testing a PDF. However, a robust test must satisfy strict constraints for each gate on the PDF to test it robustly. The input line of a gate in the PDF is referred to as its on-path input, and the remaining inputs as its off-path inputs. If the on-path input is a transition to a noncontrolling value (referred to as – ncv), then the off-inputs can be either stable at the non- controlling value (referred to as sncv) or may have a transition to the noncontrolling value (–ncv). If the on-path input is a transition to the controlling value (referred to as –cv), then all off-inputs must be stable to sncv.

A PDF fault is tested nonrobustly if there is a test pattern that detects it if it is the only PDF in the CUT. This is a more relaxed fault sensitization condition because the only constraint is that the off- inputs have a final ncv value, i.e., can be either –ncv or –ncv. A nonrobust test for a PDF may not guarantee that the transition propagates along the path. Assume that the on-input transition at a gate is –cv and the off-input is –ncv. The on-path transition actually propagates as a static hazard through the gate only if it arrives at the gate long enough after the off-input transition, for the width of the hazard to be detectable. Thus, a path must be tested nonrobustly only if there is no robust test for it. However, in some cases robust tests may exist to guarantee that no off-path inputs have delayed transitions. A nonrobust test for the PDF that is applied together with the latter tests is called validatable nonrobust because it sensitizes the PDF since the fault model assumes that all pattern for the off-input PDFs bring the same propagation delay [3].

Functionally sensitizable PDFs can be tested in the presence of multiple path delays. Such tests (referred to as functional) detect PDFs that cannot be tested by the previous methods. They detect a set of faults that is a superset of those detected by nonrobust test vectors. In particular, this sensitization condition allows for one or more gates to have a –cv transition on the on-input and the off-inputs also to have –ncv transitions. The PDF is actually sensitized by the test only when all such off-input transitions are also delayed. It has been shown that FT faults have better probability to be detected when the maximum off-input slack (or, simply, slack) is a small integer. (The slack of an off-input is defined as the difference between the stable time of the on-input signal and the stable time of the off-input signal.) PDFs that cannot be detected by any of the above conditions are referred to as functionally unsensitizable [10].

Other classifications of PDFs have been recently proposed in the literature, but they are not presented here [11,12]. Systematic PDF classification is very important when considering test pattern generation. For example, nonrobust or functional test pattern generation should be considered only when the PDF is not robustly testable. It is important to observe that ATPG does not consider actual delays on the gates under any of the existing classifications. The PDF model (as well as the TF model) generate test patterns independent of actual gate delay (or interconnect delay) values. This is appropriate in the presence of delay defects and the monotone speed-up effect [13], but also because in deep submicron it is difficult to estimate gate and interconnect delays accurately. However, ATPG tools can be enhanced so that nonrobust and functional tests are generated by considering a range on the gate and interconnect delay values. Such enhancements are not considered here.