Architecture:Input/Output Subsystem

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Input/Output Subsystem

The input/output (I/O) subsystem transfers data between the internal components (CPU and main memory) and the external devices (disks, networks, printers, keyboards, pointing devices, and scanners).

Peripheral Controllers

The CPU usually controls the I/O subsystem by reading from and writing into the I/O (control) registers. There are two popular approaches for allowing the CPU to access these I/O register, I/O instructions, and memory-mapped I/O. In an I/O instruction approach, special instructions are added to the instruction set to access I/O status flags, control registers, and data buffer registers. In a memory-mapped I/O approach, the control registers, the status flags, and the data buffer registers are mapped as physical memory locations.

Owing to the increasing availability of chip area and pins, microprocessors are increasingly including peripheral controllers on chip. This trend is especially clear for embedded microprocessors.

Direct Memory Access Controller

A direct memory access (DMA) controller is a peripheral controller which can directly drive the address lines of the system bus. The data is directly moved from the I/O data buffer registers to the main memory, rather than from the data buffer registers to a CPU register, then from CPU register to main memory. DMA controllers greatly increase the achieved transfer bandwidth of I/O operations and have become a standard feature of microprocessor systems today.

System Interconnect

System interconnect is the facilities that allow the components within a computer system to communicate with each other. There are numerous logical organizations of these system interconnect facilities. Dedicated links or point-to-point connections enable dedicated communication between components. There are different system interconnect configurations based on the connectivity of the system compo- nents. A complete connection configuration, requiring N(N – 1)/2 links, is created when there is one link between every possible pair of components. A hypercube configuration assigns a unique n-tuple {1,0} as the coordinate of each component and constructs a link between components whose coordinates differ only in one dimension, requiring N log N links. A mesh connection arranges the system components into a N-dimensional array and has connections between immediate neighbors, requiring 2N links. Switching networks are a group of switches that determine the existence of communication links among components. A cross-bar network is considered the most general form of switching network and uses a N × M two-dimensional array of switches to provide an arbitrary connection between N components on one side to M components on another side using NM switches and N + M links. Another switching network is the multistage network which employs multiple stages of shuffle networks to provide a permutation connection pattern between N components on each side by using N log N switches and N log N links.

Shared buses are single links that connect all components to all other components and are the most popular connection structure. The sharing of buses among the components of a system requires several aspects of bus control. First there is a distinction between bus masters, the units controlling bus transfers (CPU, DMA) and bus slaves, the other units (memory, programmed I/O interface).

Bus interfacing and bus addressing are the means to connect and disconnect units on the bus. Bus arbitration is the process of granting the bus resource to one of the masters. Arbitration typically uses a selection scheme based on some type of priority assignment. Fixed-priority arbitration gives every master a fixed priority, and dynamic-priority arbitration such as round-robin ensures that every master becomes the most favorable at one point in time.

Bus timing refers to the method of communication among the system units and can be classified as either synchronous or asynchronous. Synchronous bus timing uses a shared clock that defines the time other bus signals change and stabilize. Clock sharing by all units allows the bus to be monitored at agreed time intervals and action taken accordingly. However, the synchronous system bus must operate at the speed of the slowest component. Asynchronous bus timing allows units to use different clocks, but the lack of a shared clock makes it necessary to use extra signals to determine the validity of bus signals. The use of these signals to determine the validity of bus signals is called handshaking protocols, which typically reduce the achievable transfer bandwidth via the bus.

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