An Exploration of Hardware Architectures for Face Detection

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Introduction

Face detection is defined as the process of identifying all image regions that contain a face regardless of the position, the orientation, and the environment conditions in the image. A common mistake people make is to confuse it with face recognition. However, when recognizing faces, the recognition process already knows that an image contains a face. The problem now shifts into identifying the person to whom the particular face belongs [1–5]. As a result face detection has been a major research topic both in academia and industry, and the popularity of the topic appears in a wide range of applications and fields. From security to identification systems, face detection plays a primary role. It is the primary step toward face recognition [6] and serves as a forestep toward multiple applications such as identification, monitoring, and tracking. Face detection algorithms have been developed through the years, and have improved drastically both in terms of performance and speed. However, with today’s design technology, we are given the chance to perform face detection at a higher level, in the real-time domain and independent of image and environment variations. Face detection so far has been extensively done using software. With the transistor technology entering the nanometer era however, and the improvement of the detection algorithms, we are able to shift the detection stage in the hardware domain, which offers several advantages [5]. Hence, a fast hardware implementation that can be integrated either on a generic processor or as part of a larger system, directly attached to the video source, such as a security camera or a robot’s camera becomes desirable.

Software face detection methods have reached a very high level of both effectiveness and detection rate, as well as a condition-invariant level, where detection can be performed under harsh environments. However, the state-of-the-art software face detection can achieve up to 15 image frames per second (fps) [7] under favorable circumstances, and as such is not quite suitable for real-time deployment. A problem with almost all of these detection algorithms for real-time support is the complexity of the preprocessing and filtering stages that the image goes through before the detection stage [5,7–9]. With the improvement of digital cameras and digital image-processing algorithms, however, the task of hardware face detection is attainable.

This chapter outlines the advances in hardware face detection and introduces two widely accepted face detection algorithms and their respective hardware implementations. We present an FPGA- and an appli- cation specific integrated circuit (ASIC)-based implementation of a neural network-based face detection algorithm, and an architecture for the extremely fast AdaBoost algorithm proposed by Viola and Jones [7]. Through the description of both algorithm implementations, this chapter illustrates the issues and challenges in designing both hardware platforms. Section 83.2 introduces the transformation from software implementations to the hardware implementations, highlighting the design decisions that need to be made. Section 83.3 illustrates the differences in the design of a face detection system targeting different hardware platforms, by presenting two alternate implementations of a neural network-based face detection, an FPGA-based implementation, and an ASIC-based implementation. Section 83.4 shows how the algorithm choice impacts the design decision-making by illustrating the design of an architecture to implement the AdaBoost algorithm. The AdaBoost algorithm differs largely from the neural network algorithm, as it is a feature-based algorithm rather than an image-based algorithm. Section 83.5 summarizes and concludes the chapter by emphasizing the important design issues and comparing the two algorithmic approaches in hardware.

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