VLSI Architectures for Forward Error-Control Decoders:Low-Density Parity Check (LDPC) Decoder Architectures

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Low-Density Parity Check (LDPC) Decoder Architectures

LDPC codes were introduced by Gallager in his seminal work in 1963 [4], and have largely been ignored since then until the successful introduction of turbo codes by Berrou et al., in 1993 [65]. With this renewed interest, several researchers rediscovered LDPC codes and began to investigate codes on graphs in conjunction with

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iterative decoding. Long LDPC codes with iterative decoding have been shown to almost achieve capacity within a fraction of decibels [66], [67]. These discoveries have promoted LDPC codes as strong competitors to turbo codes in many communication and storage systems where high reliability is required.

This section focuses on the VLSI design aspects of LDPC decoders. After introducing LDPC codes in Section 82.5.1, two iterative decoding message-passing algorithms for LDPC codes are discussed in Section 82.5.2. In Section 82.5.3, several architectures for the message computation kernels employed by the decoding algorithm are presented and used in the decoder architectures presented in Section 82.5.4. Finally, Section 82.5.5 extends the discussion to repeat-accumulate codes.

LDPC Codes

An LDPC code is a linear block code defined by a sparse parity-check matrix HmXn with m parity-check equations on n codeword bits with k = n - m information bits. An LDPC code is typically described by a bipartite Tanner graph [68] whose adjacency matrix is H having n bit nodes and m check nodes corresponding to the n columns and m rows of H, respectively (see Figure 82.23). A bit node uj is connected to rj check nodes and a check node vi is connected to ci bit nodes, where rj and ci are called the node degrees. Equivalently, the jth column of H has rj ones, and the ith row has ci ones. If all bit- node degrees and all check-node degrees are uniform, the code is said to be regular, otherwise it is called an irregular LDPC code. In general, the graph edges are defined randomly by a p X p “edge” permuter, where p = ån r . Two graph parameters relevant to performance are the girth or length of the shortest cycle in the graph and diameter or maximum length of the shortest path in the graph. The code length n and the randomness of the edge permuter play an important role in the decoder design of an LDPC code. The encoding complexity of LDPC codes is quadratic in the code length n.

Much of the research on LDPC codes has focused on explicit construction methods of bipartite Tanner graphs with large girth. Architecture-aware LDPC (AA-LDPC) codes are a class of structured LDPC codes with large girth oriented toward an efficient decoder implementation [69]. The parity-check matrix of an AA-LDPC code is divided into S ´ S submatrices, where each submatrix is either the zero matrix or a binary permutation matrix as shown in Figure 82.24(a). Equivalently, the bit nodes and check nodes in an AA-LDPC Tanner graph are grouped into clusters of size S such that if one node from a cluster connects to a node from another cluster, then there exist distinct connections between all nodes from

VLSI Architectures for Forward Error-Control Decoders-0128

both clusters (see Figure 82.24(b)). The connections between two clusters are done according to the permutation of the corresponding submatrix in H.

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