Timing and Signal Integrity Analysis:Noise Analysis

Noise Analysis

In digital circuits, nodes that are not switching are at the nominal values of the supply (logic 1) and ground (logic 0) rails. In a digital system, noise is defined as a deviation of these node voltages from their stable high or low values. Digital noise should be distinguished from physical noise sources that are common in analog circuits (e.g., shot noise, thermal noise, flicker noise, and burst noise) [35]. Since noise causes a deviation in the stable logic voltages of a node, it can be classified into four categories:

(1) high undershoot noise reduces the voltage of a node that is supposed to be at logic 1; (2) high overshoot noise which increases the voltage of a logic 1 node above the supply level (Vdd); (3) low overshoot noise increases the voltage of a node that is supposed to be at logic 0; and (4) low undershoot noise which reduces the voltage of a logic 0 node below the ground level (Gnd).

Sources of Digital Noise

The most common sources of noise in digital circuits are crosstalk noise, power supply noise, leakage noise and charge-sharing noise [36].

Crosstalk Noise

Crosstalk noise is the noise voltage induced on a net that is at a stable logic value due to interconnect capacitive coupling with a switching net. The net or wire that is supposed to be at a stable value is called the victim net. The switching nets that induce noise on the victim net are called aggressor nets. Crosstalk noise is the most common source of noise in deep submicron digital designs because, as interconnect wires get scaled, coupling capacitances become a larger fraction of the total wire capacitances [23]. The ratio of the width to the thickness of metal wires reduces with scaling, resulting in a larger fraction of the total capacitance of the wire being contributed by coupling capacitances. Several examples of func- tional failures caused by crosstalk noise are given in the next section.

Power Supply Noise

This refers to noise on the power supply and ground nets of a design that is passed onto the signal nets by conducting transistors. Typically, the power supply noise has two components. The first is produced by IR-drop on the power and ground nets due to the current demands of the various gates in the chip (discussed in the next section). The second component of the power supply noise comes from the RLC response of the chip and package to current demands that peak at the beginning of a clock cycle. The first component of power supply noise can be reduced by making the wires that comprise the power and ground network wider and denser. The second component of the noise can be reduced by placing on-chip decoupling capacitors [37].

Charge-Sharing Noise

Charge-sharing noise is the noise induced at a dynamic node due to charge redistribution between that node and the internal nodes of the gate [32]. To illustrate charge-sharing noise, let us again consider the two-input domino NAND gate of Figure 63.9(a). Let us assume that during the first evaluate phase shown in Figure 63.9(b), both nodes x and x1 are discharged. Then, during the next precharge phase, let us assume that the input a is low. Node x will be precharged by the PMOS transistor MP, but x1 will not and will remain at its low value. Now, suppose CK turns high, signaling the beginning of another evaluate phase. If during this evaluate phase, a is high but b is low, nodes x and x1 will share charge resulting in the waveforms shown in Figure 63.9(b): x will be pulled low and x1 will be pulled high. If the voltage on x is reduced by a large amount, the output inverter may switch and cause the output node y to be wrongly set to a logic high value. Charge-sharing in a domino gate is avoided by precharging the internal nodes in the NMOS evaluate tree during the precharge phase of the clock. This is done by adding an anti- charge sharing device such as MNc in Figure 63.9(c) which is gated by the clock signal.

Leakage Noise

Leakage noise is due to two main sources: subthreshold conduction and substrate noise. Subthreshold leakage current [32] is the current that flows in MOS transistors even when they are not conducting (off). This

current is a strong function of the threshold voltage of the device and the operating temperature. Subthresh- old leakage is an important design parameter in portable devices since battery life is directly dependent on the average leakage current of the chip. Subthreshold conduction is also an important noise mechanism in dynamic circuits where, for a part of the clock cycle, a node does not have a strong conducting path to power or ground and the logic value is stored as a charge on that node. For example, suppose that the inputs a and b in the two-input domino NAND gate of Figure 63.9(a) are low during the evaluate phase of the clock. Due to subthreshold leakage current in the NMOS evaluate transistors, the charge on node x may be drained away, leading to a degradation in its voltage and a wrong value at the output node y. The purpose of the half latch device MPfb is to replenish the charge that may be lost due to the leakage current.

Another source of leakage noise is minority carrier back injection into the substrate due to bootstrap- ping. In the context of mixed analog-digital designs, this is often referred to as substrate noise [38]. Substrate noise is often reduced by having guard bands, which are diffusion regions around the active region of a transistor tied to supply voltages so that the minority carriers can be collected.