Timing and Signal Integrity Analysis:Crosstalk Noise Failures

Crosstalk Noise Failures

In this section, we provide some examples of functional failures caused by crosstalk noise. Functional failures result when induced noise voltages cause an erroneous state to be stored at a memory element (e.g., at a latch node or a dynamic node). Consider the simple latch circuit of Figure 63.10(a) and let us

assume that the data input d is a stable high value and the latch l has a stable low value. If the net corresponding to node d is coupled to another net e and there is a high to low transition on net e, net d will be pulled low. When e has finished switching, d will be pulled back to a high value by the PMOS transistor driving net d and the noise on d will dissipate. Thus, the transition on net e will cause a noise pulse on d. If the amplitude of this noise pulse is large enough, the latch node l will be pulled high. Depending on the conditions under which the noise is injected, it may or may not cause a wrong value to be stored at the latch node. For example, let us consider the situation depicted in Figure 63.10(b), where CK is high and the latch is open. If the noise pulse on d appears near the middle of the clock phase, then the latch node will be pulled high; but as the noise on d dissipates, latch node l will return to its correct value because the latch is open. However, if the noise pulse on d appears near the end of the clock phase as shown in Figure 63.10(c), the latch may turn off before the noise on d dissipates, the latch node may not recover, and a wrong value will be stored. A similar unrecoverable error may occur if noise appears on the clock net turning the latch on when it was meant to be off. This might cause a wrong value to be latched.

Now, let us consider the latch circuit of Figure 63.10(d) where the wire between the input inverter and the pass gate of the latch is long and subject to coupling capacitances. Suppose the latch is turned off (CK is low), the data input is high so that the node d′ is low, and a high value is stored at the latch node.

If net e transitions from a high to a low value, a low undershoot noise will be introduced on d′. If this noise is sufficiently large, the NMOS pass transistor will turn on even through its gate voltage is zero (since its gate-source voltage will become greater than its threshold voltage). This will discharge the latch node l, resulting in a functional failure.

In order to push performance, domino circuits are becoming more and more prevalent [88]. These circuits trade performance for noise immunity and are susceptible to functional noise failures. A noise-related functional failure in domino circuits is shown in Figure 63.11. Again, let us consider the two-input domino NAND gate shown in Figure 63.11(a). Let us assume that during the evaluate phase, a is held to a low value by the driving inverter, but b is high. Then, x should remain charged and y should remain low. If an unrelated net d switches high, and there is sufficient coupling between signals a and d, then a low overshoot noise pulse will be induced on node a. If the pulse is large enough, a path to ground will be created and node x will be discharged. As shown in Figure 63.11(b), this will erroneously set the output node of the domino gate to a high value. When the noise on a dissipates, it will return to a low value, but x and y are not able to recover from the noise event, causing a functional failure.

As the examples above demonstrate, functional failures due to digital noise cause circuits to malfunction. Noise analysis is becoming an important failure mechanism in deep submicron designs because of several technology and design trends. First, larger die sizes and greater functionality in modern chips result in longer wires, which makes the circuit more susceptible to coupling noise. Second, scaling of

interconnect geometries has resulted in increased coupling between adjacent wire [23]. Third, the drive for faster performance has increased the use of faster non-restoring logic families such as domino logic. These circuit families have faster switching speeds at the expense of reduced noise immunity. False switching events at the inputs of these gates are catastrophic since precharged nodes may be discharged and these nodes cannot recover their original state when the noise dissipates. Fourth, lower supply voltage levels reduce the magnitudes of the noise margins of circuits. Finally, in state-of-the-art microprocessors, many functional units located in different parts of the chip are operating in parallel and this causes a lot of switching activity in long wires that run across different parts of the chip. All of these factors make noise analysis a very important task to verify the proper functioning of digital designs.