Timing and Signal Integrity Analysis:Interconnects and Static TA

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Interconnects and Static TA

As is well known, interconnects are playing a major role in determining the performance of current microprocessors, and this trend is expected to continue in the next generation of processors [23]. The effect of interconnects on circuit and system performance should be considered in an accurate and efficient manner during static timing analysis. To illustrate interconnect modeling techniques, we will use the example shown in Figure 63.6(a) of a wire connecting a driving inverter to three receiving inverters.

The simplest interconnect model is to lump all the interconnect and receiver gate capacitances at the output of the driver gate. This approximation may greatly overestimate the delay across the driver gate since, in reality, all of the downstream capacitances are not “seen” by the driver gate because of resistive shielding due to line resistances. A more accurate model of the wire as a distributed RC line is shown in Figure 63.6(b). This is the wire model output by most commercial RC extraction tools. In Figure 63.6(b),

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node r is called the root of the interconnect and is driven by the driver gate, and the other end points of the wire at the inputs of the receiver gate are called sinks of the interconnect and are labeled s1, s2, and s3. Interconnects have two main effects: (1) the interconnect resistance and capacitance determines the effective load seen by the driving gate and therefore its delay, and (2) due to non-zero wire resistances, there is a non-zero delay from the root to the sinks of the interconnect — this is called the time-of-flight delay. To model the effect of the interconnect on the driver delay, we first replace the metal wire with a π-model load as shown in Figure 63.6(c) [24]. This is done by finding the first three moments of the admittance Y(s) of the interconnect at node r. It can be shown that the admittance is given by

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where R, C1, and C2 are the parameters of the π-load model. To obtain the parameters of the π-load, we equate the first three moments of Y(s) and Yˆ(s). This gives us the following equations for the parameters of the π-load model:

Timing and Signal Integrity Analysis-0234

Now, if we are using a transistor-level delay model or a pre-characterized gate-level delay model that can only handle purely capacitive loading and not π-model loads, we have to determine an effective capacitance Ceff that will accurately model the π-load. The basic idea of this method [25,26] is to equate the average current drawn by the π-model load to the average current drawn by the Ceff load. Since the average current drawn by any load is dependent on the transition time at the output of the gate and the transition time is itself a function of the load, we have to iterate to converge to the correct value of Ceff. Once the effective capacitance has been obtained, the delay across the driver gate and the waveform at node r can be obtained. The waveform at the root node is then propagated to the sink nodes s1, s2, s3 across the transfer functions H1(s), H2(s), and H3(s), respectively. This procedure is illustrated in Figure 63.6(e). If the driver waveform can be simplified as a ramp, the output waveforms at the sink nodes can be computed easily using reduced-order modeling techniques like AWE [27] and the time-of-flight delay between the root node and the sink nodes can be calculated.

Process Variations and Static TA

Unavoidable variations and disturbances present in IC manufacturing processes cause variations in device parameters and circuit performances. Moreover, variations in the environmental conditions (of such parameters are temperature, supply voltages, etc.) also cause variations in circuit performances [28]. As a result, static TA should consider the effect of process and environmental variations. Typically, statistical process and environmental variations are considered by performing analysis at two process corners: best- case corner and worst-case corner. These process corners are typically represented as different device model parameter sets, and as the name implies, are for the fastest and slowest devices. For gate-level static TA, gate characterization is first performed at these two corners yielding two different gate delay models. Then, static TA is performed with the best-case and worst-case gate delay models. Long path constraints (e.g., latch set-up and performance or speech constraints) are checked with the worst-case models and short path constraints (e.g., latch hold constraints) are checked with the best-case models.

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