Switched-Capacitor Filters:Implementation Aspects

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Implementation Aspects

The arguments presented so far have to be implemented in actual integrated circuits. Such implementations have to minimize the effects of the nonidealities of the actual blocks, which are capacitors, switches, and opamps. The capacitor behavior is quite stable, apart capacitance nonlinearities which affect the circuit performance only as a second-order effect.

In contrast, switches and opamp must be properly designed to operate in the SC system. The switches must guarantee a minimum conductance to ensure a complete charge transfer within the available time slot. For the same reason, the opamps must ensure large-DC gain, large unity-gain bandwidth, and large slew rate. For instance, in Figure 62.18 the ideal output waveform of an SC network is shown by a solid line, while the more realistic actual waveform is illustrated by a dotted line. The output sample is updated during phase f1, while it is held (at the value achieved at the end of phase f1) during phase f2 . In phase f1, the output value moves from its initial to its final value. The slowness of this movement is affected by switches conductance, opamp slew rate, and opamp bandwidth.

The transient response of the system could be studied using the linear model of Figure 62.19, where the conductive switches are replaced by their on-resistance Ron, and the impulsive charge injection is replaced by a voltage step. The assumption of a complete linear system should allow to study exactly the system evolution. In this case the circuit time-constants depend on input branch (tin = 2RonCs), opamp frequency response and feedback factor.

Nonlinear analysis is however necessary when opamp slew rate occurs. This analysis is difficult to be carried out and optimum performance can be achieved using computer simulations. Usually, for typical device models, 10% of the available time slot (i.e., Ts/2) is used for slew rate, while 40% is used for linear settling.

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Integrated Capacitors

Integrated capacitors in CMOS technology for SC circuits are mainly realized using poly1–poly2 structure, whose cross section is shown in Figure 62.20. This capacitor implementation guarantees linear behavior over a large signal swing. The main drawbacks of integrated capacitors are related to their absolute and relative inaccuracy, and to their associated parasitic capacitance.

The absolute value of integrated capacitors can change ±30% from its nominal value. However the matching between equal capacitors can be the order of 0.2%, provided that proper layout solutions are adopted (in close proximity, with guard rings, with common centroid structure). The matching of two capacitors with different C values can be expressed with the standard deviation of their ratio sC , which is correlated with the standard deviation of the ratio between two identical capacitors sC1 by

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This model can be used to evaluate the robustness of the SC system performance with respect to random capacitor variations using a Monte Carlo analysis.

The plates of poly1–poly2 capacitor of C present a parasitic capacitance toward the substrate, as shown in Figure 62.20. Typically, this capacitance is about 10% of C for the bottom plate (cp1 = C/10), and is 1% of C for the top plate (cp2 = C/100). To reduce the effect of these parasitic capacitances in the transfer function of the SC systems, it is useful to connect the top plate to the opamp input node, and the bottom plate to low impedance nodes (opamp output nodes or voltage sources). In addition in Figure 62.20, a n-well, biased with a clean voltage VREF, is placed under the poly1–poly2 capacitor to reduce noise coupling from the substrate, through parasitic capacitance.

MOS Switches

The typical situation during sampling operation is shown in Figure 62.21(a) (this is the input branch of the integrator of Figure 62.8[a]). The input signal Vi is sampled on the sampling capacitor Cs to have Vc = Vi. In Figure 62.21(b) the switches are replaced by a single-NMOS device which operates in triode region with an approximately zero voltage drop between drain and source. The switch on-resistance Ron can be

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where VG is the amplitude of the clock driving phase, mn the electron mobility, Cox the oxide capacitance, and W and L are the width and length of MOS device. Using VDD = 5 V (i.e., VG = 5 V), the dependence of Ron on the input voltage is plotted in Figure 62.22(a). This means that if Ron is required by the capacitor value be lower than a given value (to implement a low RonCs time constant), a limitation in the possible input swing is given. For instance, if the maximum possible Ron is 2.5 kW, the maximum input signal swing is 0–0.5 V.

To avoid this limitation a complementary switch can be used. It consists of a NMOS and a PMOS device in parallel, as shown in Figure 62.23. The PMOS switch presents a Ron behavior complementary to that of the NMOS, as plotted in Figure 62.22(b). The complete switch Ron is then given by the parallel of the two contributions which is sufficiently low for all the signal swing.

To use this solution, it requires to distribute double clock lines controlling the NMOS and the PMOS. This could be critical for SC filters operating at high-sampling frequency, also considering

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the synchronization of the two phases and of the digital noise from the distribute clocks which could reduce the dynamic range.

Once a minimum conductance is guaranteed, the structure can be studied using the linear model for the MOS devices S1 and S2 that operate in triode region, resulting in the circuit of Figure 62.24. In this case Vc follows Vi , through an exponential law with a time constant tin = Cs2Ron. Typically at least 6tin must be guaranteed in the sampling time slot to ensure sufficient accuracy. For a given sampling capac- itance value, this is achieved using switches with sufficiently low on-resistance and no voltage drop across its nodes. Large on-resistance results in long time constant and incomplete settling, while voltage drop results in an incorrect final value. MOS technology allows the implementation of analog switches satis- fying both the previous requirements.

Transconductance Amplifier

The SC technique appears to be the natural application of available CMOS technology design features. This is true also for the case of the opamp design. In fact, SC circuits require an infinite input opamp impedance, as it is the case of opamp using a MOS input device. In contrast, CMOS opamps are particularly efficient when the load impedance is not resistive and low, but only capacitive, as is the case of SC circuits. In addition, SC circuits allows to process full swing (rail-to-rail) signal and is possible for CMOS opamp. The main requirements to be satisfied by opamp remain the bandwidth, the slew rate and the DC gain.

clip_image038The bandwidth and the slew rate must be sufficiently large to guarantee the accurate settling for all the signal steps. The opamp gain must be sufficiently large to ensure a complete charge transfer. A trade- off between large DC gain (achieved with low-current and/or multistage structure) and large bandwidth (obtained at high-current and/or simple structure) must be optimized. For this case the use of mixed technology (like BiCMOS) could help the proper design optimization.

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