Switched-Capacitor Filters:Compensation Technique (Performance Improvements)

Compensation Technique (Performance Improvements)

SC systems usually operate with a two-phase clock in which the opamp is “really” active only during one phase, while during the other phase is “sleeping”. Provided that the opamp output node is not read during the second phase, this nonactive phase could be used to improve the performance of the SC systems, as shown in the following [15]. 1/f noise and offset can be reduced with correlated double sampling (CDS) or chopper technique. Similar structures are also able to compensate the error due to a finite gain of the operational amplifier. In contrast, proper structures are able to reduce the capacitor spread occurring in particular situations (high-Q or large time constant filters). Finally, double-sampled technique can be used to increase the sampling frequency of the SC system by a factor of 2.

CDS Offset-Compensated SC Integrator

The extra phase available in a two-phase SC system can be used to reduce opamp offset and 1/f noise effect at the output. A possible scheme is shown in Figure 62.31 [16], and operates as follows. Capacitor Cof is used to sample during f1 the offset Voff as it appears in the inverting node of the opamp close with unitary feedback. During f2 the inverting node is still at a voltage very close to Voff , since the bandwidth of Voff is assumed to be very small with respect to the sampling frequency. Capacitor Cof maintains the charge on its armatures and acts like a battery. Thus node X is a good virtual ground, independent of the opamp offset. In the same way also the output signal, read only during f2, is offset-independent. The

effect of this technique can be simulated using the value of the first-order cell of the previous example (i.e., Cf = 15.92, and Cs = Cd = 1), and Cof = 1. The transfer function Vo/Voff is shown in Figure 62.32. At low frequency, the Voff is highly rejected, while this is not the case of the standard (uncompensated) integrator. The main problem of this solution is due to the unity feedback operation of the structure during phase f1. This requires the stability of the opamp, which could consume high power.

Chopper Technique

An alternative solution to reduce offset 1/f noise at the output is given by the chopper technique. It consists of placing one SC mixer for frequency Fs/2 at the opamp input and one similar at the opamp output. This action does not affect white noise. In contrast, offset and 1/f noise are shifted to around Fs/2, not affecting anymore the frequencies around DC, where the signal to be processed is supposed to be.

This concept is shown for a fully differential opamp in Figure 62.33. In Figure 62.34 the input-referred noise power spectral density (PSD) without and with chopper modulation are shown. The white noise level (wnl) is not affected by the chopper operation and remains constant. It will be modified by the folding of the high-frequency noise, as described previously.

This technique is particularly advantageous for SC systems since the mixer can be efficiently implemented with SC technique as shown in Figure 62.35.

Finite-Gain-Compensated SC Integrator

In the opamp design, a trade-off between opamp DC gain and bandwidth exists. Therefore, when a large bandwidth is needed, a finite DC gain necessarily occurs, reducing SC filter performance accuracy. To avoid this the available extra phase can be used to self-calibrate the structure with respect to the error due to the opamp finite gain. In the literature several techniques have been proposed. The major part of them are based on the concept of using a preview of the future output samples to precharge a capacitor placed in series to the opamp inverting input node to create a “good” virtual ground (as for offset cancellation). The various approaches differ on how they get the preview and how they calibrate the new virtual ground. For the different cases, they can be effective on a large bandwidth [17,18], on a small bandwidth [19,20], or on a passband bandwidth [21]. As an example for this kind of compen- sation, one of the earliest proposed scheme is reported in Figure 62.36.

The opamp finite gain makes the opamp inverting input node to be different from the virtual ground ideal behavior and to assume the value -Vo/Ao, where Vo is the output value and Ao the opamp DC gain. In the scheme of Figure 62.36, the future output sample is assumed to be close to the previous sample, sample of Cg1. This limits the effectiveness of this scheme to signal frequencies f for which this

assumption is valid, i.e., for f /Fs << 1. The circuit operates as follows. During f1, auxiliary capacitor Cg1 samples the output while during f2, Cg1 is used to precharge Cg2 to -Vo/Ao, generating a good virtual ground at node X.

In Figure 62.37 the frequency response of different integrators are compared. Line I refers to an uncompensated integrator with Ao = 100; line II refers to the uncompensated integrator with Ao = 10,000. This line matches with line III, which corresponds to the compensated integrator with Ao = 100. Finally, line IV shows the frequency response of the ideal integrator. From this comparison, the compensation effect is to achieve Ao performance with an opamp gain similar to that achieved with an opamp gain Ao2.

Alternative solutions to the opamp gain compensation are based on the use of a replica amplifier matched with the main one. Also in this way the effectiveness of the solution is to achieve performance accuracy relative to an opamp DC gain of Ao2.

The Very-Long Time-Constant Integrator

In the design of very-long time-constant integrators using the scheme of Figure 62.8(a), typical key points to be considered are the following:

• The capacitor spread: if the pole frequency fp is very low with respect to the sampling frequency Fs, then the capacitor spread S = Cf /Cs of a standard integrator (Figure 62.8[a]) will be very large. This results in large die area and reduces performance accuracy for poor matching.

• The sensitivity to the parasitic capacitances: proper structure can reduce capacitor spread. They however suffer from the presence of parasitic capacitance. Parasitic-insensitive or at least parasitic- compensated designs should then be considered.

• The offset of the operational amplifier: offset compensations are needed when the opamp offset contribution cannot be tolerated.

In the literature, several SC solutions have been proposed, mainly oriented in reducing the capacitor spread rather than in compensating either the parasitics or the opamp offset.

A first solution is based on the use of a capacitive T-network in a standard SC integrator, as shown in Figure 62.38 [22]. The operation of the sampling T-structure is to realize a passive charge partition with the capacitors Cs1, and Cs2 + Cs3. The final result is that only the charge on Cs3 is injected into the virtual ground. Therefore the effect of this scheme is that Cs is replaced with the Cs_equiv given by the expression

the standard spread from S to S . However, for the Nagaraj’s integrator the opamp is used on both phases, disabling the possibility of using double-sampled structure.

It is, finally, possible to combine a long-time-constant scheme with an offset-compensated scheme to obtain a long-time-constant offset-compensated SC integrator [15].

Double-Sampling Technique

If the output value of the SC integrator of Figure 62.8(b) is read only at the end of f2, the requirement for the opamp to settle can be relaxed. For the integrator of Figure 62.8(b), the time available for the opamp to settle is Ts/2. The equivalent double-sampled structure is shown in Figure 62.40. The capacitor values for the two structures are the same, and thus they implement the same transfer function. The time evolution for the two structures are compared in Figure 62.41. For the double-sampled SC integrator, the time available for the opamp to settle is doubled.

This advantage can be used in two ways. First, when a high sampling frequency is required, if the opamp cannot settle in Ts/2, an extra time allows to reach the speed requirement (i.e., the double-sampling technique is used to increase the sampling frequency). Second, also at low sampling frequency when the power consumption must be strongly reduced, a smaller bandwidth to be guaranteed by the opamp reduces its power consumption.

The cost of the double-sampled structure is the doubling of all the switched capacitors. In addition, in the case of a small mismatch between the two parallel paths, mismatch energy could be present around Fs/4 [24].