RF Communication Circuits:System Level RF Design

Introduction

During the last decade of the last century, the world of wireless communications started to grow rapidly. Today, cellular handsets are the largest consumer market in the world. The main trigger was the intro- duction of digital coding and digital signal processing in wireless communications. The aggressive scaling of CMOS process technology driven by the memory and microprocessor market made CMOS a logical choice for integration of digital signal processing in wireless applications. The development of these high-performance, low-cost CMOS technologies allowed integration of enormous amount of digital functionality on one chip. This enabled the use of sophisticated modulation schemes, complex demod- ulation algorithms, and high-quality error detection and correction to produce high data rate communication channels bringing the Shannon limit in sight [1].

The RF front-ends are the interface between the antenna and the digital modem of the wireless transceiver. They have to detect very weak signals (microvolts) that come in at a very high frequency (10 GHz), and at the same time transmit high power levels (up to several Watts) at the same high frequencies. This requires high-performance analog circuits, like filters, amplifiers, and mixers that translate the incoming modulated data between the antenna and the A/D conversion and digital signal processing. Consumer electronic markets are mainly driven by low cost and low power consumption. This makes the RF front-ends the bottleneck for future wireless applications. Low cost and low power are both linked to high integration level. A high level of integration renders a significant space, cost, weight, and power reduction. A higher degree of integration requires less discrete components reducing the bill of cost of materials. Keeping signals on chip greatly reduces power consumption since less I/O drivers are needed. Many different techniques to obtain a higher degree of integration have been presented over the years [2–5]. This chapter introduces and analyzes some advantages and disadvantages and their fundamental limitations.

Parallel to the trend for further integration, there is the trend to integrate RF circuitry in CMOS technologies. While digital baseband processing has already been implemented in CMOS technology in several product generations, CMOS RF has only recently made progress. For a long time many design houses believed that complicated mixed-signal RF CMOS chips were impossible to realize. The main objective against CMOS RF was the lack of high-Q passive components and its poor noise performance. It took the persistence of some academic institutions and some pioneering firms to prove them wrong. It is clear that the full potential of RF CMOS would not have been unfolded, if only stand-alone radios were developed. CMOS RF systems-on-chip (SoC) today implement all radio building blocks including phase-locked loop (PLL), low-noise amplifier (LNA), power amplifier (PA), up- and downconversion mixers, filters, and antenna switch. Furthermore, they include all digital baseband processing circuitry and ROM memory [6,7]. This reveals the real strength of CMOS RF over other “better suited” technologies like Si bipolar, BiCMOS, and silicon germanium (SiGe). Putting together RF and baseband in one chip permits compensation of lower radio performance with less- expensive digital signal-processing circuits, making its performance competitive with SiGe radios. Together with a possible 75% reduction of discrete components, RF CMOS offers the cheapest solution if one pursues the ultimate goal: a single chip including the physical layer (PHY) as well as the media access control (MAC) together with a MAC processor, memory, and I/O such as USB ports or PCI interfaces.

RF CMOS is not a matter of just replacing bipolar transistors with their CMOS counterpart. It requires a whole new range of architectures, techniques, and a high integration level. When compared to CMOS, SiGe requires less power for a certain gain and achieves a lower noise figure. The biggest drawback of CMOS is its inferior 1/f noise performance. This will only increase with the introduction of high-K dielectric materials in the gate of future CMOS technology nodes. CMOS design engineers therefore went looking for new topologies to reduce the impact of 1/f noise on the radio performance. Another problem that had to be overcome was the lack of high-Q passive components in CMOS technology. Extra processing steps as well as innovative layout and design techniques solved this problem. First, this chapter will analyze some concepts, trends, limitations, and problems posed by technology for high-frequency design. Next, we will discuss a variety of architectures used in modern RF CMOS transceivers. In the rest of the chapter, we will take a closer look at the different building blocks that appear in a typical RF transceiver. We will split this into downconversion, upconversion, and frequency synthesis.

In a final section, we will take a look at RF CMOS’s last barrier: RF power transmission. As CMOS gate lengths shrink, lower voltages are tolerated at the transistor terminals. High-quality impedance converters must therefore be placed between the antenna and the transistor’s drain for high power transmissions. These are not available yet in integrated form. One of the major bottlenecks in CMOS PAs is combining high efficiency with high linearity. For high-power transmission, designers are obliged to bias the PA high in its saturation region where linearity is low. Therefore, today’s integrated PAs are limited to constant envelope modulation schemes like GSM. High-efficiency PAs still remain out of reach for modulation schemes with large peak-to-average power ratios like OFDM. This chapter will discuss some circuit techniques to circumvent this bottleneck bringing the ultimate goal of a single-chip CMOS solution that is compatible with all standards and is capable of adapting itself a step closer to reality.

System Level RF Design

General Overview

One of the main challenges facing the RF design engineer originates from the transmission medium used by RF systems. RF systems communicate through air by means of electromagnetic waves. Using air as transmission medium has one great advantage: it gives the transceiver the ability to be mobile. However, there are some disadvantages to this high degree of freedom. There exists only one medium i.e., air which is consequently used by numerous applications. An overview of these applications and the part of the spectrum they use can be found on the website of the National Telecommunications and Information Administration (NTIA) [8]. As a result, RF systems operate in a filled spectrum. Receivers will not only detect the desired signals indigenous to the application, but will also pick up other signals that will consequently be amplified and detected. These unwanted detected signals are called interferers. If the interferer is sufficiently large, it can corrupt the desired signals preventing them from being properly demodulated and understood. On the transmit side of the application, unwanted signals are generated and transmitted. They are picked up by other applications and can distort their performance. These unwanted transmitted signals are called spurious signals. It is the designer’s responsibility to keep these inteferers and spurious signals as low as possible. Based on the former discussion, it is clear that one needs a regulator to manage the use of this spectrum. In the United States this is done using a dual organizational structure; NTIA manages the Federal Government’s use of the spectrum while the Federal Communications Commission (FCC) [9] manages all other uses.

Signals travelling through air also suffer from attenuation. There are several mechanisms causing attenuation such as free-space dispersion, fading, and multipath. These mechanisms depend heavily on the distance between the transmitter and receiver, the frequency of transmission, and the environment. Discussion of these mechanisms, however, is beyond the scope of this text. More information concerning these topics can be found in [10,11]. As a result of these mechanisms, one can expect the received signal power to have a large variation since the distance between the transmitter and receiver can change considerably owing to the mobility. Performance of RF communication systems is also degraded by thermal noise. Noise, like in other communication systems, is the limiting factor when dealing with weak signals. The noise energy consists of two contributors. First, there is thermal noise which is determined by temperature and bandwidth and is beyond the control of the designer. Second, there is system noise. This kind of noise can, within limits, be controlled by the designer to allow a certain minimum level of signal power to be detected by the system.

In the following sections we will take a closer look at the challenges described in the former discussion. First, we will take a brief look at the tools and metrics RF designers use to describe and control the performance of their system in the presence of interferers and noise. We will end this section with a discussion of some commonly used transceiver architectures.

RF System Performance Metrics

As described in Section 60.2.1, the lowest signal power level that can be detected correctly by a receiver is limited by noise. The lowest power level that can be detected is usually called the receiver sensitivity. The receiver sensitivity is related to the signal-to-noise ratio (SNR) at the end of the receiver chain (baseband). The SNR at the baseband is determined by the bit error rate (BER) required by the appli- cation. It is usually expressed in terms of Eb/No. Eb is the energy per received bit and No is the noise power density received together with the bit. The relation between Eb/No and BER depends on the modulation scheme used in the application (e.g., GMSK in GSM) and is beyond the scope of this text. More information can be found in Ref. [12]. The SNR can be expressed as a function of Eb/No as follows:

where fb is the bit rate and B the receiver noise bandwidth. Note that the overall system noise at baseband N is the sum of the thermal and circuit noise. This leads to a figure of merit that describes the circuit’s performance. It is called noise figure when expressed in decibel and noise factor otherwise. Noise factor or figure is a measure of the excess noise that is contributed by the circuit to the overall noise and is defined as the ratio between the SNR at the input of the receiver (SNRi) and the SNR at the output of the receiver (SNRo):

in which NFi are the noise factors of successive building blocks and Gi is their respective power gain. One can easily conclude from Eq. (60.3) that building blocks earlier in the receiver chain have a larger contribution to the overall noise figure than blocks at the end of the chain. This is the reason behind the use of an LNA at the input of an RF receiver. The large power gain combined with a low noise figure will relax the noise specifications for the following blocks. This principle is explained in Figure 60.1. If an LNA is omitted and the mixer is put directly behind the antenna, the signal is drowned in the mixer noise and the sensitivity will be low. The power gain of the LNA however pushes the antenna signal above the noise floor of the mixer. As long as the output noise of the LNA is greater than the input noise of the mixer, the sensitivity is fully determined by the NF of the LNA.

RF systems often operate in an interference-limited environment. Interference can also reduce receiver sensitivity. It is therefore more correct to describe the receiver sensitivity by its signal to (noise plus interference) ratio S/(N + I) also known as the signal to noise and distortion ratio (SNDR). One of the mechanisms by which interference limits the performance is nonlinearity. It can reduce the signal power as well as increase interference. Large signals can saturate the receiver resulting in a gain compression,

which reduces the signal power S. In contrast, two large interfering signals can, owing to nonlinearity produce cross-product terms that overlap with the desired signal, increasing the interference I. This cross- product generation is called intermodulation distortion (IMD). Nonlinearity performance is typically characterized by small-signal linearity described by second- and third-order intercept points (IP2 and IP3) and large-signal linearity described by the 1 dB compression point. Usually, balanced topologies are used in attenuating the second-order harmonics. Consequently, third-order nonlinearity will become the limiting factor. These concepts will be explained with help of Figure 60.2. Gain compression is charac- terized by the 1 dB compression point (P-1dB) and is used to evaluate the ability of the system to cope with strong input or interference signals often referred to as blockers. It is defined as the input power for which the gain drops by 1 dB. By identifying the strongest signals at each stage of the design, one can calculate the required 1 dB compression point for each block in a receiver chain. As mentioned earlier, nonlinearity not only causes gain compression, but also generates IMD. This is produced by any pair of blockers that lie near the desired signal. If two tones at f1 and f2 are applied to a nonlinear block, frequencies are produced not only at f1 and f2, but also at 2f1 - f2, 2f2 - f1, 3f1, 3f2, and so on. f1, f2, 3f1, and 3f2 are not important since they lie far outside the frequency band of interest and can therefore be filtered out. 2f1 - f2 and 2f2 - f1 however are potential problems as they can overlap with the desired signal band and remain unaffected by filtering. The ratio of any of the two cross products is called third- order IMD (IMD3). The output power of the intermodulation products grows at a faster rate than that of the desired signal itself. Therefore, it follows that at a certain input power, the output power of the intermodulation signals will surpass the desired signal. The input power level, where this takes place is called the input-referred third-order intercept point (IIP3). The output power at this point is called the output-referred third-order intercept point (OIP3). Note that this is an imaginary point since gain compression occurs before this point is reached. If the receiver consists of different building blocks, one may want to know the contribution of the different building blocks to the overall linearity performance. One can prove that in case of a cascaded system

where IIP3i are the input-referred third-order intercept points of the successive building blocks and Gi their respective power gain. One can conclude that contrary to noise (see Eq. (60.3)), the last blocks in the receiver chain has the largest influence on the overall linearity of the receiver. Eqs. (60.3) and (60.4) reveal a first trade-off. High gain at the input reduces noise constraints in the rest of the chain, but increases the linearity requirements.

A last origin of distortion is due a nonideal local oscillator (LO) signal driving the mixers. In practice, the spectrum of an oscillator is never pure. There is always a certain amount of energy present close to the ideal LO frequency at w0 + Dw. This can translate nearby frequency signals overlapping with the desired signal also deteriorating the SNDR of the system. A figure of merit to describe this nonideal LO behavior is called the LO phase noise and is defined as the ratio of the power present in a 1 Hz band at a certain offset frequency Dw from the carrier frequency w0 to the carrier power:

In this section, a brief overview of some common transceiver structures will be discussed and contrasted with one another. The discussion will be restricted to the heterodyne transceiver, the zero-intermediate frequency (IF) or direct-conversion transceiver, and the low-IF transceiver. There exist numerous other types of transceivers, but their properties can be understood by looking at these three structures as they are all variations or combinations of the same. First, the different receiver architectures will be discussed followed by their transmitter equivalents.

The heterodyne receiver has been the dominant choice among RF systems for many decades. The reason behind this is its high performance and adaptability to different standards. Figure 60.4 shows the operation of a heterodyne receiver. The broadband antenna signal is first fed to a highly selective RF filter (band select filter), that suppresses all interferers outside the desired application band. An LNA boosts the desired signal above the mixer noise floor and an LO generates a signal located at an offset frequency fIF from the desired signal. The result is that the following signals are downconverted by the mixer to fIF:

Not only is the desired signal mapped onto IF but also another signal called the image or mirror signal. This signal can corrupt the information content is such a way that the information is irreparable. To avoid this, an image reject filter is inserted before the mixer. This way, a highly attenuated version of the image signal overlaps with the desired signal, preventing the irreparable corruption of the information content of the signal. Figure 60.3 summarizes this operation. From Eq. (60.6) and (60.7), one can see that the center of the image signal is located at a distance 2fIF from the desired signal. The choice of fIF therefore determines the requirements for the image reject filter. If a very low fIF is chosen, a very high- quality filter is needed to suppress the image frequency. To relax the filter specifications, fIF is usually chosen relatively high and a series of downconversion steps are performed. The heterodyne structure is then referred to as the superheterodyne receiver.

The heterodyne or superheterodyne receiver features a single-path topology. Mismatch between different parts is not a issue here. Moreover, LO-feedthrough in the mixer is not a problem, since the desired signal is never close to the LO-frequency. In Figure 60.4 it can also be seen that the channel selection is done before the AGC-A/D structure. They will therefore only need to handle a limited dynamic range.

A drawback of the structure, however, is that all critical functions are realized with passive devices. Owing to the high demands posed upon these structures, they are mostly implemented off-chip. The integratability of the heterodyne transceiver is therefore rather low. This incurs an additional material cost. Moreover, the insertion loss of the passive filters needs to be compensated by a higher gain on-chip

to retain the required SNR. Since the filters need to be driven at low impedance (e.g., 50 W), one has the choice between using complex impedance transformation structures or using low-output impedance buffers. Using low-output impedance drivers, however, comes at the cost of an extra amount of power consumption.

The integratability, however, can dramatically be improved if one could find a way of getting rid of the external high-quality filters. This means looking for a way of suppressing the image frequency without filters. A first solution to this problem is obvious. Make the image signal the desired signal or chose fIF = 0. This solution is called the zero-IF receiver or direct conversion receiver [13,14]. Another solution is related to the first one and is called the low-IF topology [3]. This topology takes advantage of the fact that the channels in the direct neighborhood of the desired channel—the adjacent channels—are usually much weaker than the desired signal and the signals lying further away. Furthermore, these frequency bands are usually regulated in the application specifications or by the FCC. So, if an IF-frequency is chosen such that the image frequency falls into this lower power bands, less image rejection is needed to retain the required SNR. Figure 60.5 shows the architecture of both a direct or zero-IF receiver and a low-IF receiver. The only difference between the two can be found in the choice of IF-frequency. In a zero-IF receiver, the desired channel is converted to DC and a mirrored version of the channel itself is superimposed onto

the clean version of the signal. In a low-IF receiver, the desired signal is downconverted to a low, non- zero IF, e.g., half the channel bandwidth, such that the mirror signal is the adjacent channel. The antenna signal is first passed through a band select filter. An LNA boosts the signal above the mixer noise floor. So far, there is no difference in the heterodyne receiver. After the LNA, however, the signal is fed to two different signal paths. The two signal paths are then downconverted by two mixers that are steered by two LO signals that are spaced 90° apart. The interstage filter has now become obsolete since the mirror signal will be neutralized by recombining the two signal paths after downconversion. This type of downconversion is called quadrature downconversion. Since the image signal and the desired signal are separated in the DSP, the real channel selection and image rejection is done in the digital back-end. This is an advantage, since the digital domain is the natural biotope of CMOS. Since the image rejection and channel selection no longer rely on high-quality filtering, no external filters are required, therefore, one does not have to cope with their inevitable loss and one does not need low-impedance drivers. This allows low-power operation. However, the spreading of the signal over two independent signal paths has some drawbacks. The topology relies heavily on the symmetry between the two paths, every mismatch between the two paths will lead to a deterioration of the image suppression and an increased corruption of the desired information content. Although one could think that image rejection requirements are more relaxed for a zero-IF receiver since the image signal is a mirrored version of the desired signal, this is not exactly true. For low-IF receivers, the image signal can be considered as noise for the desired signal, since there is no correlation at all between the two bands. For zero-IF receivers, there is a strong correlation between the image and the desired signal leading to a distortion of the desired signal. The required image suppression is therefore dependent on the type of modulation that is used in the system. When a QAM- type modulation is used, one can calculate that the required image rejection for zero-IF is 20–25 dB while 32 dB rejection is required for low-IF systems [15]. As the desired signals in both receivers are located at low frequencies (DC in case of zero-IF), the signal is susceptible to 1/f noise and DC-offset. Complicated feedback structures can get rid of the DC-offset, however, owing to the finite time constants in those loops, part of the signal is also canceled by the feedback. This can corrupt the signal in an unacceptable way. Low-IF topologies are less vulnerable. As long as the DC-offset does not saturate the A/D converters, there is no signal degradation. Owing to the absence of filtering in the RF part, the A/D converters, however, have to deal with larger dynamic ranges. Fortunately, as the signals are at low frequencies, oversampled converters that allow higher accuracies can be used.

The same topologies exist for the transmitter side of the transceiver. The heterodyne as well as the direct upconversion transmitter will be discussed. They are depicted in Figure 60.4 and Figure 60.5. The early upconversion architectures were in fact multistage architectures. They employed a number of mixing stages and intermediate frequencies. The main advantage of this type of systems is that only one D/A converter is needed. Quadrature modulated signals are therefore generated in the digital domain. This topology puts high demands on the D/A converter since it must deliver signals at a higher IF frequency. In contrast, the DSP must be able to deliver perfectly matched I/Q signals. This approach requires the use of high-quality passives, multiple LOs. The same conclusions can be drawn as in the receiver. Owing to the large number of external components, integratability is limited and power consumption will be high. Another implementation of this multistage architecture includes the use of two D/A converters. Quadrature modulated signals are then generated in the analog domain. Since they are generated at low frequencies, quadrature matching is superior. However, multiple RF filters are still needed, giving rise to a higher cost and power consumption. The topology, however, is not vulnerable to one of the main problems in the direct conversion architecture, oscillator pulling caused by the PA owing to the fact that the PA output spectrum is far away from the voltage controlled oscillator (VCO) frequency. Thus, the main problem in direct upconversion circuits is addressed. In direct conversion transmitters, the trans- mitted carrier frequency is equal to the LO frequency. As can be seen in Figure 60.5, modulation and upconversion occur in the same circuit. The I/Q quadrature modulator takes the baseband (or low-IF) input signal and upconverts it directly to the desired RF frequency. This eliminates the need for RF passives and limits the number of amplifiers, mixers, and LOs. The simplicity of the architecture makes it an obvious choice when high integration levels are demanded. However, as mentioned before, the circuit suffers from one major drawback, the disturbance of the LO by the PA. This phenomenon is explained in more detail in Refs. [16,17]. As the LO frequency lies in the transmit band, high demands are put on the LO/RF isolation. The system is also susceptible to I/Q mismatch errors, even the least phase mismatch or amplitude difference between I and Q path will result in distortion in the spectrum. However, the elimination of the IF stage in the transmitter leads to large saving in material cost and increases the robustness of the system as the number of discrete components that could fail is reduced. There is not only a cost saving in material cost, the direct upconverter architecture also allows a reduction in equipment size. This makes the circuit the first choice for applications with stringent space constraints [18] .