RF Communication Circuits:Synthesizer

Synthesizer

One fundamental building block in every RF transceiver is the frequency synthesizer. The frequency synthesizer is responsible for generating the LO signal. The signal generated by the frequency synthesizer needs to be clean since low oscillator noise is crucial for the quality and reliability of the information transfer. The signal should also be programmable and fast switching to be able to address all frequency channels within the specified time frame.

Topology

Synthesizers can usually be divided into three categories: the table look-up synthesizer, the direct syn- thesizer, and the indirect or PLL synthesizer. In a table look-up synthesizer, the required sinusoidal frequency is created piece by piece using digital representations of the amplitude stored in memory at different time points of the sinusoidal waveform. The required building blocks are an accumulator that keeps track of the time, a memory containing a sine, a digital-to-analog converter (DAC), and a low-pass filter to perform interpolation of the waveform to remove high-frequency spurs. This type of synthesis is limited is frequency owing to the access time of the memory and owing to the maximum operation frequency of the high-accuracy DAC. Moreover, high-frequency spurs, generated owing to the sampling behavior of the system tend to corrupt the spectral purity of the signal. The direct frequency synthesizer employs multiplication, division, and mixing to generate the desired frequency from a single reference. By repeatedly mixing and dividing, any level of accuracy is possible. The output spectrum is as clean as the reference frequency spectrum. Very fast-frequency hopping is possible. The main disadvantages of this type of system is the difficult layout of the system, the high power consumption owing to the numerous components present, and the corrupting of the spectral purity by cross coupling between stages. For generating high frequencies, the indirect or PLL type of frequency synthesizer is often the best choice. In a PLL, the synthesized frequency is generated by locking a locally generated frequency to an external frequency. The external frequency originates from a low-frequency high-quality crystal oscillator. To generate a local signal in the PLL, a VCO is used. A simple PLL topology is shown in Figure 60.12. A PLL includes the following building blocks: a VCO, a phase/frequency detector (PD/PFD), a loop filter, and frequency divider or prescaler. The last building block is needed to derive a low frequency signal from the LO. This allows the signal to be locked to the external frequency by means of the phase detector. The phase detector is a circuit that compares the external frequency phase with the locally generated frequency phase and outputs an error voltage proportional to the phase difference. After filtering, this error signal is fed back to the VCO. This constitutes a control system. Under lock conditions, the external frequency and the locally generated frequency have a constant phase relationship.

The two signals are locked to each other, hence the name PLL. Even when a low-quality LO signal is generated, a high-quality signal can be synthesized. Owing to the phase relationship between the input and the output frequency, the output signal will have the same spectral purity as the high-quality input signal. This is due to the fact that the loop remains locked to the input phase and therefore follows the phase deviations of that signal thus taking over its phase noise. This however is only true as long as the loop dynamics can follow the input signal. The loop dynamics are mainly determined by the bandwidth of the loop. For offset frequencies below the loop bandwidth, the phase noise is determined by the phase noise of the reference signal, for frequency offsets above the loop bandwidth, the output phase noise will be determined by the phase noise of the locally generated signal.

When a programmable frequency divider is used in the loop, one can see that a set of frequencies can be synthesized. Assuming that the frequency by which the output signal is divided can be varied between N1 and N2, the output becomes

The PLL synthesizer is inherently slower than the other two types of synthesizers. The switching speed between two frequencies in Eq. (60.25) is mainly determined by the loop bandwidth. Fast switching is only possible if a high loop bandwidth is implemented. Note that the loop bandwidth will also determine the phase noise performance. One however cannot indefinitely enlarge the loop bandwidth for stability reasons. A rule of thumb is that the loop bandwidth may not exceed 10% of the reference frequency to maintain stability. The loop bandwidth will also be limited by phase noise constraints. Spurious suppression and in-band phase noise levels will ultimately determine the loop bandwidth. When a low bandwidth has to be implemented, large capacitors will be needed. The total capacitance value is mainly determined by the need for implementing a stabilizing low-frequency zero in the loop filter. This makes integration difficult as it will blow up the silicon area and therefore increases the cost. One must therefore find ways to implement small bandwidth without having to use large capacitors. One obvious way of doing this is creating a low- frequency pole through the use of a large resitance. This however will increase phase noise. Other techniques however exist. In Ref. [35] a dual-path loop filter is used. The filter consist of one active path and one passive path. Combining both will create a low-frequency zero without the need for an extra resistor and capacitor. In Ref. [36] another technique is used to create the low-frequency zero. It is created in the digital domain. The signal in the loop filter is combined with a sampled and delayed version of itself. If the required switching speed is not achieved with a PLL configuration, one can make a combination of the direct synthesizer with the indirect synthesizer. In this topology, a number of PLLs is implemented and the outputs of all are combined with mixers. Thus, it is possible to synthesize a wide frequency range with a fast switching speed. This technique has recently been adopted for use in ultrawide band systems [37]. The major drawback of this technique, however, is that single sideband mixers have to be used. This requires accurate quadrature phases in all PLLs, low harmonic distortion, and well-matched mixers.

Oscillator

As was mentioned above, the VCO is the main source of the phase noise outside the loop bandwidth. Therefore, its design is one of the critical parts of a PLL design. For the design of subgigahertz VCO, two oscillator types are often used: ring oscillators and oscillators based on a resonant tank composed of an inductor and a capacitor. The latter is referred to as an LC-tank VCO. The inductor in an LC-tank VCO can be implemented in two ways: an active implementation and a passive implementation. It can be shown [38,39] that the phase noise is inversely proportional to the power consumption. In LC-tank VCOs, the power consumption is proportional to the quality factor of the tank. Eqs. (60.26)–(60.28) show this relationship:

It is clear that for high frequency, a low power solution is only viable with an LC-tank VCO with a passive inductor. The use of a passive inductor however comes at a severe area penalty. Moreover, as was discussed in Section 60.3, high-quality integrated inductors are difficult to make. For extremely low phase noise VCOs, bondwire inductors have been investigated [38]. The main drawback of using bondwires as inductors lies in reliability and yield. It is very difficult to make two bondwires exactly the same and reproduce this several times.

Prescaler

Several structures can be used as programmable divider. Programmable counters are the easiest solutions and are available in standard cell libraries. They are however limited in operation frequency. When high frequencies need to be synthesized, one can use a so-called prescaler. A prescaler divides by a fixed ratio and can therefore operate at high frequencies because it does not have to allow for delays involved with counting and presetting. A few high-speed prescaler stages lower the speed used in the subsequent counter stages. The disadvantage is that for a certain frequency resolution, the reference frequency has to be lowered. This slows the loop down as a lower bandwidth has to be implemented to maintain stability in the loop. A solution to this resolution problem is the use of dual or multimodulus prescalers. This circuit extends the prescaler with some extra logic to allow the prescaler to divide by N and N + 1 in case of a dual-modulus prescaler and by N to N + x in case of a multimodulus prescaler. The reduction in speed of this extra circuitry can usually be limited. Figure 60.13 shows two possible implementations of a dual-modulus prescaler. Implementation (a) is a straight- forward implementation based on d-flip-flops. The critical path consists of a NAND gate and a d-flip-flop. Implementation (b) is a more complex implementation. It is based on the 90° phase relationship between the outputs of a master/slave toggle flip-flop. It contains no additional logic in the high-frequency path. The dual-modulus prescaler is as fast as an asynchronous fixed divider.

Fractional-N Synthesis

As can be concluded from Eq. (60.25), the minimal frequency resolution that can be achieved when using the topologies described previously is equal to Fref. In GSM, for example, the channels are 200 kHz spaced apart, this means that we need a frequency resolution of 200 kHz and therefore a low reference frequency.

This results in high division ratios. The in-band phase noise of a PLL is however proportional to the division ratio, large ratios mean high in-band noise. As is already explained, a low reference frequency will also result in a low PLL bandwidth and therefore a slow loop. Therefore we need a technique that enables us to use a high reference frequency and still achieve the required frequency resolution. Fractional-N synthesizers solve this problem. Figure 60.14 elucidates this. A basic fractional-N synthesizer consists, besides the standard PLL building blocks, of an accumulator and a dual modulus prescaler. By switching fast between the two division ratios, fractional divisions can be synthesized. The accumulator increases its value every reference clock cycle with a certain amount K = n2k. The dual-modulus prescaler is controlled by the accumulator overflow bit. If the accumulator overflows, the division ratio is N + 1, else it is N. On average, the dual-modulus prescaler divides K times by N + 1 and 2k - K times by N, resulting in a synthesized frequency of

This means that noninteger ratios can also be synthesized and the above-mentioned limitations on the reference frequency are not applicable. There are of course drawbacks to the technique. The major one is the generation of spurs in the output spectrum owing to pattern noise in the overflow signal. A detailed study of fractional-N synthesis however is beyond the scope of this chapter and the reader is referred to the open literature for further information. A thorough study of fractional-N synthesizers and their simulation can be found in Ref. [41].