RF Communication Circuits:Receiver

Receiver

LNA

The importance of the LNA has been explained earlier. The LNA is used to boost the received signal above the mixer noise floor. It is therefore critical that the LNA itself produces little noise. The noise figure of an LNA embedded in an 50 W system is defined as

i.e., the real output noise power (dv2/Hz) of the LNA (consisting of the amplified input noise power and all noise contributions generated in the LNA itself) divided by the amplified input power. Figure 60.9 shows some common input structures. Figure 60.9(a) shows a nonterminated common-source input stage. Figure 60.9(b) shows the same input stage, but now with an impedance matching at the input. Figure 60.9(c) shows the common-gate input structure and finally, Figure 60.9(d) shows a transimpedance amplifier structure that is commonly used for wideband applications. Their respective noise figures can

indicating that a low-noise figure requires a large transconductance in the first stage. To generate this transconductance with high power efficiency, we need to bias the transistor in the region with a large transconductance efficiency i.e., low Vgs - Vt. This, however, will result in a large gate-source capacitance limiting the bandwidth of the circuit. Together with the 50 W source resistance, the achievable bandwidth is limited by

This means that a low-noise figure can only be achieved by making a large ratio between the frequency performance of a transistor, represented by fT and the theoretical bandwidth f3dB of the circuit. Note that the f3dB used here is not the same as the one used is Section 60.3. Since fT is proportional to Vgs - Vt, a low-noise figure requires a large Vgs - Vt and associated with it a large power drain. Only by going to deep submicron technologies will fT become large enough to achieve low-noise figures for gigahertz operation with low power consumption. In practice, the noise figure is further optimized by using noise and source impedance matching. These matching techniques often rely on inductors to cancel out parasitics by creating resonant structures. This boosts the maximum operation frequency to higher frequencies. More information concerning the design and optimization of common source LNAs can be found in Refs. [31,15].

At high antenna input powers, the signal quality mainly degrades owing to in-band distortion com- ponents that are generated by third-order intermodulation in the active elements. Long-channel transis- tors are generally described by a quadratic model. Consequently, a one-transistor device ideally only suffers from second-order distortion and produces no third-order intermodulation products. As a result, high IIP3 values should easily be achieved. When transistor lengths shrink however, third-order inter- modulation becomes more important.

To start the analysis of the main mechanisms behind third-order intermodulation one needs an approximate transistor model. A drain current equation that is strongly related to the SPICE level 2 and 3 models is

where q stands for the mobility degradation owing to transversal electrical fields (surface scattering at the oxide–silicon interface) and the m0/(Leffvmaxn) models, the degradation owing to longitudinal fields (electrons reaching the thermal saturation speed). As the q-term is small in today’s technologies, it can often be neglected relative to the longitudinal term. It can be seen from Eq. (60.18) that for large values of Vgs - VT , the current becomes a linear function of Vgs - VT . The transistor is then conducting in the velocity saturation region. For smaller values of Vgs - VT, the effect of Q consists apparently in linearizing the quadratic relationship, but in reality, the effect results in an intermodulation behavior that is worse than in the case of quadratic transistors. The second-order modulation will be lower, but is realized at the cost of a higher third-order intermodulation. The following equations can be found by calculating the Taylor expansions of the drain current around a certain Vgs - VT value [32]:

denotes the relative amount of velocity saturation. The transit voltage Vsv depends only on technology parameters. For deep submicron processes, this voltage becomes even smaller than 300 mV, which is very close to the Vgs - VT at the boundary of strong inversion. The expressions for IIP2 and IIP3 are normalized to 0 V db m, the voltage that corresponds to a power of 0 dB in a 50 W resistor. For a given Leff, the IIP3-value of a transistor is only a function of the gate overdrive voltage. Figure 60.11 plots the IIP2 and IIP3 as a function of the gate overdrive voltage for different values of Q. It can be seen that for a certain value of Vgs - VT , the IIP2 increases for increasing Q (decreasing gate lengths), which proves

(b) third-order intermodulation point.

the former statements. The picture becomes a bit more complicated when looking at the IIP3 plot. For practical values of Q, one can distinguish two regions in the Vgs - VT domain. For high gate overdrive voltages, deep submicron transistors clearly exhibit better linearity because the saturation voltage becomes lower and the transistor will reach velocity saturation earlier. Short-channel transistors there- fore offer a maximum amount of linearity at a given power supply and require minimum Vgs - VT for a given IIP3. In contrast, for low overdrive voltages, short-channel transistors perform worse. Thus, to ensure a certain amount of linearity, one has to bias the transistors at a high enough overdrive voltage or apply some linearizing feedback technique (e.g., source degeneration). It can be shown that for the same equivalent gm and the same distortion level, the required DC current is lower when local feedback is provided at the source. It is realized, however, at the cost of a larger transistor and this can compromise the amplifier bandwidth.

Downconverter

The most frequently used topology for a multiplier is the multiplier with cross-coupled variable transconductance differential stages. The use of this topology or related topologies (e.g., based on the square law) in CMOS is limited for high-frequency applications. Two techniques are used in CMOS: the use of the MOS transistor as a switch and the use of the MOS transistor in the linear region.

The technique often used in CMOS downconversion for its ease of implementation is subsampling on a switched-capacitor amplifier [33,34]. Here, the MOS transistor is used as a switch with a high input bandwidth. The desired signal is commutated via these switches. Subsampling is used to be able to implement these structures with a low-frequency op-amp. The switches and the switched-capacitor circuit run at a much lower frequency (comparable to an IF frequency or even lower). The clock jitter must however be low such that the high-frequency signals can be sampled with a high enough accuracy. The disadvantage of subsampling is that all signals and noise on multiples of the sampling frequency are folded upon the desired signal. The use of a high-quality HF filter in combination with the switched- capacitor subsampling topology is therefore absolutely necessary.

In Ref. [3] a fully integrated quadrature downconverter is presented. The circuit requires no external components, nor does it require tuning or trimming. It uses a double-quadrature structure, which renders a very high performance in quadrature accuracy. The downconverter topology is based on the use of MOS transistors in the linear region. By creating a virtual ground, a low-frequency op-amp can be used for downconversion. The MOS transistor in the linear region results in a very high linearity for both the RF and the LO signal.