Register Transfer Level Hardware Description with Verilog:Verilog in Digital Design Flow

Verilog in Digital Design Flow

Verilog syntax and language constructs are designed to facilitate description of hardware components for simulation and synthesis. In addition, Verilog can be used to describe test benches, specify test data, and monitor circuit responses. Figure 88.1 shows a simulation model that consists of a design and its test bench in Verilog. Simulation output is generated in the form of a waveform for visual inspection or data files for machine readability.

After a design passes basic functional validations, it must be synthesized into a netlist of components of a target library. Constructs used for verification of a design, or timing checks and timing specifications are not synthesizable. A Verilog design that is to be synthesized must use language constructs that have a clear hardware correspondence. Figure 88.2 shows a block diagram specifying the synthesis process.

The output of synthesis is a netlist of components of the target library. Often synthesis tools have an option to generate this netlist in Verilog. In this case, the same testbench prepared for presynthesis simulation can be used with the netlist generated by the synthesis tool.

Modules

The entity used in Verilog for description of hardware components is a module. A module can describe a hardware component as simple as a transistor or a network of complex digital systems. Modules begin with the module keyword and end with endmodule. A design may be described in a hierarchy of other modules. The top-level module is the complete design, and modules lower in the hierarchy are the design’s components. Module instantiation is the construct used for bringing a lower level module into a higher level one. Figure 88.3 shows a hierarchy of several nested modules.

As shown in Figure 88.4, in addition to the module keyword, a module header also includes the module name and list of its ports. Following the module header, its ports and internal signals and variables are declared. Specification of the operation of a module follows module declarations.

Operation of a module can be described at the gate level, using Boolean expressions at the behavioral level or a mixture of various levels of abstraction. Figure 88.5 shows three ways of describing a module. Module simple1a in Figure 88.5 uses Verilog’s gate primitives, simple1b uses concurrent statements, and simple1c uses a procedural statement.

The subsections that follow describe details of module ports and description styles. In the examples in this chapter, Verilog keywords and reserved words are shown in bold; Verilog is case-sensitive. It allows letters, numbers and special character “_” to be used for names. Names are used for modules, parameters, ports, variables, and instance of gates and modules.

Module Ports

Following the name of a module is a set of parenthesis with a list of module ports. This list includes inputs, outputs, and bidirectional input/output lines. Ports may be listed in any order. This ordering can

only become significant when a module is instantiated, and does not affect the way its operation is described. Top-level modules used for testbenches have no ports.

Following the module header, ports of a module are declared. In this part, size and direction of each port listed in the module header are specified. A port may be input, output, or inout. The latter type is used for bidirectional input/output lines. Size of vectored ports of a module is also declared in the module port declaration part. Size and indexing of a port are specified after its type name within square brackets. Figure 88.6 shows an example circuit with scalar, vectored, input, output, and inout ports. Ports named a, and b are 1-bit inputs. Ports av and bv are 8-bit inputs of acircuit. The set of square brackets that follow the input keyword applies to all ports that follow it. Port w of acircuit is declared as a 1-bit output, and wv is an 8-bit bidirectional port of this module.

In addition to port declarations, a module declarative part may also include wire and variable decla- rations that are to be used inside the module. Wires (that are called net in Verilog) are declared by their types, wire, wand or wor; variables are declared as reg. Wires are used for interconnections and have properties of actual signals in a hardware component. Variables are used for behavioral descriptions and are very much like variables in software languages. Figure 88.7 shows several wire and variable declarations. Wires represent simple interconnection wires, buses, and simple gate or complex logical expression outputs. When wires are used on the left-hand sides of assign statements, they represent outputs of logical structures. Wires can be used in scalar or vector form. Figure 88.8 shows several examples of wires used on the right- and left-hand sides of assign statements.

In the vector form, inputs, outputs, wires, and variables may be used as a complete vector, part of a vector, or a bit of the vector. The latter two are referred to as part-select and bit-select.

Logic Value System

Verilog uses a four-value logic value system. Values in this system are 0, 1, Z, and X. Value 0 is for logical 0, which in most cases represents a path to ground (GND). Value 1 is logical 1 and it represents a path to supply (Vdd). Value Z is for float, and X is used for uninitialized, undefined, unknown, and value conflicts. Values Z and X are used for wired-logic, buses, initialization values, tri-state structures, and switch- level logic.

For more logic precision, Verilog uses strength values in addition to logic values. Our dealing with Verilog is for design and synthesis, and these issues will not be discussed here.