PLL Circuits:PLL Techniques

Introduction

What’s and Why Phase-Locked?

Phase-locked loop (PLL) is a circuit architecture that causes a particular system to track with another one. More precisely, PLL synchronizes a signal (usually a local oscillator output) with a reference or an input signal in frequency as well as in phase.

Phase locking is a useful technique that can provide effective synchronization solutions in many data transmission systems such as optical communications, telecommunications, disk drive systems, and local networks, in which data are transmitted in baseband or passband. In general, only data signals are transmitted in most of these applications, namely, clock signals are not transmitted to save hardware cost. Therefore, the receiver should have some mechanisms to extract the clock information from the received data stream to recover the transmitted data. The scheme is called a timing recovery or clock recovery.

The cost of electronic interfaces in communication systems increases as the data rate gets higher. Hence, high-speed circuits are the critical issue of the high data rate systems implementation, and the advanced VLSI technology plays an important role in cost reduction for the high-speed communication systems.

Basic Operation Concepts of PLLs

Typically, as shown in Figure 61.1, a PLL consists of three basic functional blocks: a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). PD detects the phase difference between the VCO output and the input signal, and generates a signal proportional to the phase error. The PD output contains a DC component and an AC component, the former is accumulated and the latter is filtered out by the loop filter. The loop filter output that is near a DC signal is applied to the VCO. This almost DC control voltage changes the VCO frequency toward a direction to reduce the phase error between the input signal and the VCO. Depending on the type of loop filter used, the steady-state phase error will be reduced to zero or to a finite value.

PLL has an important feature, which is the ability to suppress both the noises superimposed on the input signal and generated by the VCO. In general, the more narrow bandwidth the PLL has, the more effectively the filtering of the superimposed noises can be achieved. Although a narrow bandwidth is better for rejecting large amounts of the input noise, it also prolongs the settling time in the acquisition process. Then, the error of the VCO frequency cannot be reduced rapidly. So there is a trade-off between jitter filtering and fast acquisition.

Classification of PLL Types

Different PLL types have been built from different classes of building blocks. The first PLL ICs appeared around 1965 and were purely analog devices. In the so-called linear PLLs (LPLLs), an analog multiplier (four-quadrant) is used as the PD, the loop filter is built of a passive or an active resistor-capacitor (RC) filter, and the VCO is used to generate the output signal of the PLL. In most cases, the input signal to this linear PLL is a sine wave, whereas the VCO output signal is a symmetrical square wave.

The classical digital PLL (DPLL) uses a digital PD such as an XOR gate, a JK-flipflop, or a phase- frequency detector (PFD). The remaining blocks are still the same as LPLL. In many aspects, the DPLL performance is similar to the LPLL.

The function blocks of the all digital PLL (ADPLL) is implemented by purely digital circuits, and the signals within the loop are digital too. Digital versions of the PD are the same as DPLL. The digital loop filter is built of an ordinary up-downcounter, N-before-M counter or K-counter [1]. The digital coun- terpart of the VCO is the digital-controlled oscillator (DCO) [2,3].

In analogy to filter designs, PLLs can be implemented by software such as a microcontroller, micro- computer or digital signal processing (DSP), this type of PLL is called software PLL (SPLL).

PLL Techniques

Basic Topology

A PLL is a feedback system that operates and minimizes the phase difference between two signals. The PD works as a phase-error detector and an amplifier. It compares the phase of the VCO output signal uo(t) with the phase of the reference signal ui(t) and develops an output signal ud(t) that is proportional to the phase error qe. Within a limited range, the output signal can be expressed as

where kd (in V/rad) represents the gain of the PD.

The output signal ud(t) of the PD consists of a DC component and a superimposed AC component. The latter is undesired and removed by the loop filter (LPF). Thus, the LPF generates an almost DC control voltage for the VCO to oscillate at the frequency equal to the input frequency.

How the building blocks of a basic PLL work together will be explained in the following. At first, assume both the waveforms of input signal and VCO output are rectangular. Furthermore, it is assumed that the angular frequency wi of the input signal ui(t) is equivalent to the central frequency wo of the VCO signal uo(t). Now a small positive frequency step is applied to ui(t) at t = t0 (shown in Figure 61.2). ui(t) accumulates the phase increments faster than uo(t) of VCO does. If the PD can response wider pulses increasingly, a higher DC voltage is accordingly generated at the LPF output to increase the VCO frequency. Depending on the type of the loop filter that will be discussed later, the final phase error will be reduced to zero or a finite value.

It is important to note from the descriptions above that the loop locks only after the two conditions are satisfied: (1) wi and wo are equal and (2) the phase difference between the input ui(t) and the VCO output uo(t) settles to a steady-state value. If the phase error varies with time so fast that the loop is unlocked, the loop must keep on the transient process, which involves both “frequency acquisition” and “phase acquisition.”

To design a practical PLL system, it is required to know the status of the responses of the loop if (1) the input frequency is varied slowly (tracking process), (2) the input frequency is varied abruptly (lock-in process), and (3) the input and the output frequencies are not equal initially (acquisition process). Using linear PLL as an example, these responses will be shown in Sections 61.2.3–61.2.5.

Loop Orders of the PLL

Figure 61.3 shows the linear model of a PLL. According to the control theory, the close-loop transfer function of PLL can be derived as

parameters (t and k = kokd) available to achieve fast tracking as well as the noise suppression. Then three loop parameters (wn, z, k) must be determined. If it is necessary to have a large DC loop gain and a very narrow bandwidth, the loop will be severely underdamped and the transient response will be poor.

In practice, there are three basic types of loop filter: passive lead-lag filter, active lead-lag filter, and active PI (proportional and integral) filter. The characteristics of the three types of loop filter and their effects on the PLL will be described in Section 3.3. Besides, a high-order filter is used for critical applications, because it provides better noise filtering, initial acquisition, and fast tracking. However, it is diffcult to design a high-order loop due to some problems such as loop stability.

Tracking Process

The linear model of a PLL shown in Figure 61.3 is suitable for analyzing the tracking performance of a PLL that is almost in lock, only with a small phase error. If the phase error changes too abruptly, the PLL fails to lock, and a large phase error is induced even though the change happens only momentarily. The unlock condition is a nonlinear process that cannot be analyzed via the linear model. The acquisition process will be described in Section 61.2.5.

At first, consider that a step phase error expressed as qi(t) = Dqu(t) is applied to the input. The Laplace transform of the input is qi(s) = Dq/s that is substituted into Eq. (61.3) to get

where qv is called the velocity error or static phase error [4]. In practice, the input frequency almost never agrees exactly with the VCO free-running frequency, that is, usually there is a frequency difference Dw between the two. From Eq. (61.8), if the PLL has a high DC loop gain, that is, kdkoF(0) � Dw, the steady- state phase error corresponding to a step frequency error input approaches to zero. This is the reason that a high gain loop has a good tracking performance. Now the advantage of a second-order loop using an active loop filter with high DC gain is evident. The active lead-lag loop filter with a high DC gain will make the steady-state phase error approach to zero and the noise bandwidth narrow simultaneously, which is impossible in a first-order loop.

If the input frequency is changed linearly with time at a rate of Dw, that is,qi (t) = 1 Dwt , qi (s) = Dw/s .

According to a high gain loop and applying the final value theorem of Laplace transform, it is derived

For qe to be zero, it is necessary to make F(s) be a form of G(s)/s2, where G(0) ¹ 0. G(s)/s implies that the loop filter has two cascade integrators. This results in a third-order loop. To eliminate the static acceleration error, a third-order loop is very useful for some special applications such as satellite and missile systems.

On the basis of Eq. (61.9), a large natural frequency wn is used to reduce the static tracking phase error in a second-order loop, however, a wide natural frequency has an undesired noise filtering performance. In the contrast, the zero tracking phase error for a frequency ramp error is concordant with a small loop bandwidth in a third-order loop.

All the preceding analysis on the tracking process is under the assumption that the phase error is relatively small and the loop is linear. If the phase error is large enough to make the loop drop out of lock, the linear assumption is invalid. For a sinusoidal-characteristic PD, the exact phase expression of Eq. (61.8) should be

The hold range is the frequency range in which a PLL is able to maintain lock statically. Namely, if input frequency offset exceeds the hold range statically, the steady-state phase error would drop out of the linear range of the PD and the loop loses lock. kv is the function of ko, kd and F(0). The DC gain F(0) of the loop filter depends on the filter type. Therefore, it is important to make a loop filter have a high DC gain for extending the hold range. Referring to the characteristics of the three basic types of loop filter described in Section 61.3.3, the hold range DwH can be kokd, kokdka, and ¥ for passive lead-lag filter, active lead-lag filter, and active PI filter, respectively. The hold range expressed in Eq. (61.12) is not correct when some other components in PLL are saturated earlier than the PD. When the PI filter is used, the real hold range is actually determined by the control range of the VCO.

Considering the dynamic phase error qa in a second-order loop, the exact expression for a sinusoidal characteristic PD is

which implies that the maximum change rate of the input frequency is wn. If the rate exceeds wn , the loop will fall out of lock.

Lock-in Process

The lock-in process is defined as PLL locks within one single beat note between the input and the output (VCO output) frequency. The maximum frequency difference between the input and the output that PLL can lock within one single beat note is called the lock-in range of the PLL.

Figure 61.4 shows a case of PLL lock-in process that a frequency offset Dw is less than the lock-in range, and the lock-in process happens. Then PLL will lock within one single beat note between wi and wo. In Figure 61.4, the frequency offset Dw between input (wi) and output (wo) is larger than the lock-in range, hence the lock-in process will not take place, at least not instantaneously.

Suppose the PLL is unlocked initially. The input frequency wi is wo + Dw. If the input signal vi(t) is a sine wave and given by

The high-frequency components can be filtered out by the loop filter. The output of the loop filter is given by

Acquisition Process

Suppose that the PLL does not lock initially, the input frequency is wi = wo + Dw, where wo is the initial frequency of VCO. If the frequency error Dw is larger than the lock-in range, the lock-in process will not occur. Consequently, the output signal ud(t) of the PD shown in Figure 61.5(a) is a sine wave that has the frequency of Dw. The AC PD output signal ud(t) passes through the loop filter. Then the output uf(t) of the loop filter modulates the VCO frequency. As shown in Figure 61.5(b), when wo increases, the frequency difference between wi and wo becomes smaller and vice versa. Therefore, the phase detector output ud(t) becomes asymmetric when the duration of positive half-periods of the PD output is larger than the negative ones. The average value ud (t ) of the PD output therefore becomes positive slightly. Then the frequency of VCO will be pulled up until it reaches the input frequency. This phenomenon is called a pull-in process.

Because the pull-in process is a nonlinear behavior, the mathematical analysis is quite complicated. According to the results of Ref. [1], the pull-in range and the pull-in time depend on the type of loop filter. For an active lead-lag filter with a high gain loop, the pull-in range is

Aided Acquisition

The PLL bandwidth is always too narrow to lock a signal with large frequency error. Furthermore, the frequency acquisition is slow and impractical. Therefore, there are aided frequency-acquisition techniques to solve this problem such as the frequency-locked loop (FLL) and the bandwidth-widening methods.

The FLL, which is very much similar to a PLL, is composed of a frequency discriminator, a loop filter, and a VCO. PLL is a coherent mechanism to recover a signal buried in noise. An FLL, in contrast, is a noncoherent scheme that cannot distinguish the phase error between input signal and VCO signal. Therefore, an FLL can only be useful to provide the signal frequency which exactly synchronizes with the reference frequency (RF) source.

The major difference between PLL and FLL is the PD and the frequency discriminator. The frequency discriminator is the frequency detector in the FLL. It generates a voltage proportional to the frequency difference between the input and the VCO. The frequency difference will be driven to zero in a negative feedback fashion. If a linear frequency detector is employed, it can be shown that the frequency- acquisition time is proportional to the logarithm of the frequency error [6]. In the literature, some frequency detectors like quadricorrelator [7], balance quadricorrelator [8], rotational frequency detector [9], and frequency delimiter [10] are disclosed.

PLL Noise Performance

In high-speed data recovery applications, a better performance of the VCO and the overall PLL itself is desired. Consequently, the random variations of the sampling clock, so-called jitter, is the critical performance parameter.

Jitter sources of PLL in the case of using a ring VCO mainly come from the input and the VCO itself. The ring oscillator jitter is associated with the power supply noise, the substrate noise, 1/f noise, and the thermal noise. The former two noise sources can be reduced by fully differential circuit structure. 1/f noise, in contrast, can be rejected by the tracking capability of the PLL. Therefore, the thermal noise is the worst noise source. From the analysis of Ref. [11], the one-stage RMS timing jitter error of the ring oscillator normalized to the time delay per stage can be shown as

where Iss is the rail current of the delay cell, To the output period of the VCO. On the basis of Eq. (61.25), designing a low jitter VCO, (Vgs – Vt) should be as large as possible. For fixed delay and fixed current, a lower gain of each stage is better for jitter performance, but the loop gain must satisfy the Barkhausen criterion. From the viewpoint of VCO jitter, a wide bandwidth of PLL can correct the timing error of the VCO rapidly [12]. If the bandwidth is too wide, the input noise jitter may be so large that dominates the jitter performance of the PLL. Actually this is a trade-off.

For a PLL design, the natural frequency and the damping factor are the key parameters to be determined by designers. If the input signal-to-noise ratio (SNR)i is defined, then the output signal-to-noise ratio (SNR)o can be obtained [4]:

Therefore wn and z can be designed to satisfy the (SNR)o requirement.

Beside the system and the circuit designs, jitter can be reduced in the board level design. Board jitter can be alleviated by better layout and noise-decoupling schemes, such as appending proper decouple and bypass capacitances.