PLL Circuits:PLL Applications

PLL Applications

Clock and Data Recovery

In data transmission systems such as optical communications, telecommunications, disk drive systems, and local networks, data are transmitted on baseband or passband. In most of these applications, only data signals are transmitted by transmitter, but clock signals are not transmitted to save hardware cost. Therefore, the receiver should have some schemes to extract the clock information from the received data stream and to regenerate transmitted data using the recovered clock. This scheme is called timing recovery or clock recovery.

To recover the data correctly, the receiver must generate a synchronous clock from the input data stream, the recovered clock must synchronize with the bit rate (the baud of data). The PLL can be used to recover the clock from the data stream, but there are some special design considerations. For example, because of the random nature of data, the choice of PFDs is restricted. In particular, three-state PD is not proper, because when there are no transitions in the data stream, the PD interprets that the VCO frequency is higher than the data frequency and remains its output in the “down” state, which makes the PLL to lose lock as shown in Figure 61.23. Thus, the choice of PFD for random binary data requires a careful examination over whether data transitions are absent. One useful method is the rotational frequency detector described in Ref. [9]. The random data also cause the PLL to introduce undesired phase variation in the recovered clock; it is called timing jitter and is an important issue in the clock recovery.

Data Format

Binary data are usually transmitted in an NRZ format as shown in Figure 61.24(a) because of the consideration of bandwidth efficiency. In NRZ format, each bit has a duration of TB (bit period). The signal does not tend to zero between adjacent pulses representing 1’s. It is shown in Ref. [21] that the corresponding spectrum has no line component at fB = 1/TB, and most of the spectrum of this signal lines below fB/2. The term “non-return-to-zero” distinguishes itself from another data type called “return-to-zero”(RZ) as shown in Figure 61.24(b), where the signal tends to zero between consecutive bits. Therefore, the spectrum of RZ data has a frequency component at fB. For a given bit rate, RZ data need wider transmitting bandwidth, and therefore NRZ data are preferable when channel or circuit bandwidth is a concern.

Owing to the lack of a spectral component at the bit rate of NRZ format, a clock recovery circuit may lock to spurious signals or fail to lock at all. Thus, a nonlinear process for the NRZ data is essential to create a frequency component at the baud rate.

Data Conversion

One way to recover the clock signal from the NRZ data is to convert it into an RZ-like data that has a frequency component at the bit rate, and then recover clock from data using a PLL. Transition detection is one of the methods to convert NRZ data into RZ-like data. As illustrated in Figure 61.25(a), the edge detection requires a mechanism to sense both positive and negative data transitions. In Figure 61.25(b), NRZ data is delayed and compared with itself by an exclusive-OR gate, therefore the transition edges are detected. In Figure 61.26, the NRZ data Vi is first differentiated to generate pulses corresponding to each transition. These pulses are made to be all positive by squaring the differentiated signal Vi . The result is that the signal Vi′ looks just like RZ data where pulses are spaced at an interval of TB.

Clock Recovery Architecture

On the basis of different PLL topologies, there are several clock recovery approaches. Here, the early-late and the edge-detector-based methods will be described.

Figure 61.27 shows the block diagram of the early-late method. The waveforms for the case in which the input lags the VCO output are shown in Figure 61.28, where the early integrator integrates the input signal for the early-half period of the clock signal, and holds it for the remainder of the clock signal. In contrast, the late integrator integrates the input signal for the late-half period of the clock signal and

holds it for the next early-half period. The average difference between the absolute values of the late hold and the early hold voltage generated from a low-pass filter gives the control signal to adjust the frequency of the VCO. As mentioned above, this method is popular for rectangular pulses. However, there are some drawbacks in this method. Since this method relies on the shape of pulses, a static phase error can be introduced if the pulse shape is not symmetric. In high-speed applications, this approach requires a fast settling integrator that limits the operating speed of the clock recovery circuit and the acquisition time cannot be easily controlled.

The most widely used technique for clock recovery in high-performance, wideband data transmission applications is the edge-detection-based method. The edge-detection method is used to convert data format such that the PLL can lock the correct baud frequency. More details have been described in Section 61.4.1.2. There are many variations of this method depending on the exact implementation of each PLL loop component. The “quadricorrelator” introduced by Richman [7] and modified by Bellisio [22] is a frequency-difference discriminator and has been implemented in a clock recovery architecture. Figure 61.29 [23] is a phase-FLL using edge-detection method and quadricorrelator to recover timing information from NRZ data. As shown in Figure 61.29, the quadricorrelator follows the edge-detector with a combination of three loops sharing the same VCO. Loops I and II form a FLL that contains the quadricorrelator for frequency detection. Loop III is a typical PLL for phase alignment. Since the phase- locked loops and FLLs share the same VCO, the interaction between two loops is a very important issue.

As described in Ref. [23], when ω1 ≈ ω2, the DC feedback signal produced by loops I and II approaches zero and loop III dominates the loop performance. A composite FLL and PLL is a good method to achieve fast acquisition and a narrow PLL loop bandwidth to minimize the VCO drift. Nevertheless, because the wideband FLL can response to noise and spurious components, it is essential to disable FLL when the frequency error gets into the lock-in range of the PLL to minimize the interaction. More clock recovery architectures are described in Refs. [14,16,17,24–26].

Delay-Locked Loop

Two major elements for adjusting the timing are VCO and voltage-controlled delay line (VCDL). Figure 61.30 shows a typical delay-locked loop (DLL) [27,28] that replaces the VCO of a PLL with a VCDL. The input signal is delayed by an integer multiple of the signal period because the phase error is zero when the phase difference between Vin and Vo approaches multiple of the signal periods. The VCDL usually consists a number of cascaded gain stages with variable delay. Delay lines, unlike ring oscillators, cannot generate a signal, therefore it is diffcult to make frequency multiplication in a DLL. In a VCO, the output “frequency” is proportional to the input control voltage. The phase transfer function contains a pole, which is H(s) = ko/s (ko is the VCO gain). In a VCDL, the output “phase” is proportional to the control voltage, and the phase transfer function is H(s) = kVCDL. So the DLL can be easily stabilized with a simple first-order loop filter. Consequently, DLLs have much more relaxed trade- offs among gain, bandwidth, and stability. This is one of the two important advantages over PLLs. Another advantage is that delay lines typically introduce much less jitter than VCO [12]. Because a delay chain is not configured as a ring oscillator, there is no jitter accumulation since the noise does not contribute to the starting point of the next clock cycle.

A typical application of DLL is to synchronize the clock edges of subsystems within a digital system to access the bus between subsystems. Figure 61.31 shows modern digital systems that use synchronous communication to achieve high-speed signaling to and from the bus between the subsystems. Subsystems that communicate synchronously use a clock signal as a timing reference so that data can be transmitted and received with a known relationship to this reference. A diffculty in maintaining this relationship is that process, voltage, and temperature variations can alter the timing relationship between the clock and data signals of subsystems, resulting in reduced timing margins. Figure 61.32 shows that on the left side the data valid window (the time over which data can be sampled reliably by the receiver) can be large at low-signaling speeds. Even in the presence of a substantial shift in the data valid window across operational extremes, the resulting data valid window can still be large enough to transmit and receive data reliably. Unfortunately, the variations in process, voltage, and temperature can result in the loss of the data valid window when the signal speed is increased as also shown on the right side of Figure 61.32. This problem gets worse as signaling speeds increase, limiting the ability of subsystems to communicate data at higher speeds.

The function of DLLs and PLLs to synchronize a signal with a reference or an input signal in frequency as well as in phase can be used to maintain such a fixed timing relationship between signals of subsystems. Figure 61.33 shows how a DLL is used to maintain the timing relationship between a clock signal and an output data signal. The PD detects phase differences between the clock and output data and sends control information through a low-pass filter to a variable delay line that adjusts the timing of the internal clock to maintain the desired timing relationship. The PD must account for the timing characteristics of the output logic and output driver. This is important since it estimates the phase differences between the clock and the data driven by the output driver, where the timing relationships of subsystems are changed over time due to the process, voltage, and temperature variations. Maintaining the timing relationships between the clock and output data with DLLs and PLLs results in improved timing margins as shown in Figure 61.34. Then, the important limitation to increasing signaling speeds is addressed.

Frequency Synthesizer

A frequency synthesizer generates any of the number of frequencies by locking a VCO to an accurate frequency source such as a crystal oscillator. For example, RF systems usually require a high-frequency

local oscillator whose frequency can be changed in small and precise steps. The ability of multiplying a RF makes PLLs attractive for synthesizing frequencies.

The basic configuration used for frequency synthesis is shown in Figure 61.35(a). The system is capable of generating the frequency at an integer multiple of the RF. A quartz crystal is usually used as the reference clock source because of its low jitter characteristic. Owing to the limited speed of CMOS device, it is difficult to generate frequency directly in the range of GHz or more. To generate higher frequencies, prescalers are used, which are implemented with other IC technologies such as ECL. Figure 61.35(b) shows a synthesizer structure using a prescaler V, where the output frequency becomes

Because the scaling factor V is obviously �1, it is no longer possible to generate any desired integer multiple of the reference frequency. This drawback can be circumvented by using a so-called dual- modulus prescaler as shown in Figure 61.36. A dual-modulus prescaler is a divider whose division can be switched from one value to the other by a control signal. The following shows that the dual-modulus prescaler makes it possible to generate a number of output frequencies that are spaced only by one RF. The VCO output is divided by V/V + 1 dual-modulus prescaler. The output of the prescaler is fed into a “program counter” 1/N and a “swallow counter” 1/A. The dual-modulus prescaler is set to divide by V + 1 initially. After “A” pulses out of the prescaler, the swallow counter is full and changes the prescaler modulus to V. After additional “N − A” pulses out of the prescaler, the program counter changes the prescaler modulus back to V + 1 and restarts the swallow counter. Then the cycle is repeated. In this way, the VCO frequency is equal to (V + 1)A + V (N − A) = VN + A times the RF. Note that N must be higher than A. If this is not the case, the program counter would be full earlier than the 1/A and both counters would be reset. Therefore, the dual-modulus prescaler would never be switched from V + 1 to V. For example, if V = 64, then A must be in the range 0–63 such that Nmin = 64. The smallest realizable division ratio is

The synthesizer of Figure 61.36 is able to generate all integer multiples of the RF starting from Ntot = 4096. For extending the upper frequency range of frequency synthesizers but still allowing the synthesis of lower frequency, the four-modulus prescaler is a solution [1].

On the basis of the above discussions, the synthesized frequency is an integer multiple of a RF. In RF applications, the RF is usually larger than the channel spacing for loop dynamic performance considera- tions, in which the wider loop bandwidth for a given channel spacing allows faster settling time and reduces the phase jitter requirements to be imposed on the VCO. Therefore a “fractional” scaling factor is needed. Fractional division ratios of any complexity can be realized. For example, a ratio 3.7 is obtained if a counter is forced to divide by 4 in seven cycles of each group of ten cycles and by 3 in the remaining three cycles. On average, this counter divides the input frequency by 3.7 effectively.