Performance Modeling and Analysis Using VHDL and System:Mixed-Level Modeling Taxonomy

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Mixed-Level Modeling Taxonomy

The functions that the mixed-level interface must perform and the most efficient structure of the interface is affected by several attributes of the system being modeled and the model itself. To partition the mixed- level modeling space and better define the specific solutions, a taxonomy of mixed-level model classes has been developed [43]. The classes of mixed-level modeling are defined by those model attributes which fundamentally alter the development and the implementation of the mixed-level interface. The mixed- level modeling space is partitioned according to three major characteristics:

(1) the evaluation objective of the mixed-level model,

(2) the timing mechanism of the uninterpreted model, and

(3) the nature of the interpreted element.

For a given mixed-level model, these three characteristics can be viewed as attributes of the mixed- level model and the analysis effort. Figure 77.20 summarizes the taxonomy of mixed-level models.

Performance Modeling and Analysis Using VHDL and SystemC-0080

Performance Modeling and Analysis Using VHDL and SystemC-0081

Mixed-level modeling objectives. The structure and the functionality of the mixed-level interface are strongly influenced by the objective that the analysis of the mixed-level model will be targeted toward. For the purposes of this work, these objectives were broken down into two major categories:

1. Performance analysis and timing verification. To analyze the performance of the system (as defined previously) and verify that the specific component(s) under consideration meet system timing constraints. Note that other metrics, such as power consumption, could be analyzed using mixed- level models, but these were outside the scope of this classification.

2. Functional verification. To verify that the function (input-to-output value transformation) of the interpreted component is correct within the context of the system model.

Timing mechanisms. Typically, performance (uninterpreted) models are asynchronous in nature and the flow of tokens depends on the handshaking protocol. However, in modeling a system that is globally synchronous (all elements are synchronized to a global clock) a mechanism to synchronize the flow of tokens across the model can be introduced. This synchronization of the performance model will require different mixed- level modeling approaches. Thus the two types of system models that affect the mixed-level interface are:

1. Asynchronous models. Tokens on independent signal paths within the system model move asyn- chronously with respect to each other and arrive at the interface at different times.

2. Synchronous models. The flow of tokens in the system model is synchronized by some global mechanism and they arrive at the interface at the same time, according to that mechanism.

Interpreted component. The mixed-level modeling technique strongly depends upon the type of the interpreted component that is introduced into the performance model. It is natural to partition interpreted models into those that model combinational elements and sequential elements. Techniques for constructing mixed-level interfaces for models of combinational interpreted elements have been developed previously [44]. In the combinational element case, the techniques for resolving the timing across the interface were more straightforward because of the asynchronous nature of the combinational elements, and the data-abstraction problem was solved using a methodology similar to the one presented here. However, using sequential interpreted elements in mixed-level models requires more complex interfaces to solve the synchronization problem and different specific techniques for solving the data-abstraction problem. Further research into the problem of mixed-level modeling with sequential elements suggested that interpreted components be broken down into three classifications as described below:

1. Combinational elements: Unclocked (with no states) elements.

2. Sequential control elements (SCEs): Clocked elements (with states) that are used for controlling data flow, e.g., a control unit or a controller.

3. Sequential data flow elements (SDEs): Elements that include datapath elements and clocked ele- ments that control the data flow, e.g., control unit and datapath.

The major reason for partitioning the sequential elements into SDEs and SCEs is based on the timing attributes of these elements. In a SCE control input values are read every cycle and control output values (that control a datapath) are generated every cycle. In contrast, SDEs have data inputs and may have some control inputs but the output data are usually generated several clock cycles later. This difference in the timing attributes will dictate a different technique for mixed-level modeling. Because the solution for the timing and data-abstraction problem for SDE elements is more complex, and the solution for SCE elements can be derived from the solution for SDE elements, developing a solution for SDE elements was the focus of this work.

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