Oversampled Analog-to-Digital and Digital-to-Analog Converters:Practical Design Issues

Practical Design Issues

As with any design involving analog components, there are a number of circuit limitations and trade- offs in sigma-delta data converter design. The design considerations discussed in this section include kT /C noise, integrator scaling, ampliﬁer gain, and sampling nonlinearity. Also discussed in this section are the techniques of integrator reset and multilevel feedback.

kT/C Noise

In switched capacitor-based modulators, one fundamental nonideality associated with using a MOS device to sample a voltage on a capacitor is the presence of a random variation of the sampled voltage after the MOS switch opens [61–63]. This random component has a gaussian distribution with a variance of kT/C, where k is the Boltzman’s constant, C the capacitance, and T the absolute temperature. The variation stems from thermal noise in the resistance of the MOS channel as it is opening. The noise voltage has a mean power of 4kTRB, where R is the channel resistance and B the bandwidth. It is low- pass ﬁltered by its characteristic resistance and the sampling capacitor to an equivalent noise bandwidth of 1/RC. The total integrated variance will thus be kT/C, independent of the resistance of the switch.

If, in the process of developing the integrated signal, a sampling operation on n capacitors is used, then since we assume gaussian noise distribution, the variance of the eventual integrated value will be nkT/C. In the case of a fully differential integrator, where a differential signal is sampled onto two sampling capacitors and then transferred to two integration capacitors, n is 4. This effect, along with the input referred noise of the ampliﬁer, will limit the achievable noise ﬂoor of the modulator. The ﬁrst-stage sampling capacitors must be sized so as to limit this noise contribution to an acceptable level. From this starting point, and the capacitive ratios required for realizing the various integrator gains, the remaining capacitor sizes may be determined. The modulator will be much less sensitive to kT/C noise generated in integrators past the ﬁrst, and the capacitors in these integrators may be made considerably smaller.

Integrator Gain Scaling

The integration stages in Section 59.2 were discussed as ideal elements, capable of developing any real output voltage. In practice, the output voltage of real integrators is limited to at most the supply voltage of the embedded ampliﬁer. To ensure that this limitation does not adversely affect the modulator perfor- mance, a survey of the likely limit of integrator output voltages must be made for a given value of the DAC reference voltage. The modulator may be simulated over a large number of samples with a repre- sentative sinusoidal input, and a histogram of all encountered output voltages tabulated. These histograms may be expected to scale linearly with the reference voltage level. In general, this statistical survey will show that a modulator designed to realize the integrator gain constants in the ideal topologies of Sections 59.2 and 59.3 will have different ranges of expected output voltages from each of its integrators. For example, Figure 59.42 and Figure 59.43 show the simulated output voltages at the two integrators in a second-order modulator with eight- and two-level feedback, respectively. Since the largest value possible of reference level will generally mean the best-available signal-to-noise ratio for a given circuit power consumption, the integrator gain constants may be adjusted from their straightforward values so that the overall modulator transfer function remains the same, but the output voltages are scaled so that no

integrator limits the signal swing markedly before the other [11]. Figure 59.44 and Figure 59.45 illustrate the properly scaled second-order modulator examples.

Amplifier Gain

Another mechanism by which the actual characteristic of the integrator circuits fall short of the ideal is the limitation of ﬁnite ampliﬁer gain. A study of many simulations of modulators with various ampliﬁer gains [11] has shown that a modulator needs ampliﬁers with gains about numerically equal to the decimation ratio of the ﬁlter that follows it to avoid signiﬁcant noise-shaping errors. At least this is the result with perfectly linear ampliﬁers, and in practice, ampliﬁer gains often need to be at least 10 times this high to avoid distortion in the integrator characteristic due to the nonlinearity of the ampliﬁer gain characteristic.

One approach used when the simple circuits of Section 59.5.2 do not develop enough gain in a given process is the regulated cascode gain enhancement [64,65]. Figure 59.46 illustrates a typical circuit topology. This subcircuit may be substituted for the output common source ampliﬁer stages in the ampliﬁers of Figures 59.33–59.35 if the power supply voltage can accommodate its somewhat increased requirement for headroom.

Low Supply Voltages

Oversampled modulators are typically integrated on a larger chip that includes at least the digital decimation ﬁlter, and often more complex digital signal processing systems. Given the trend to lower supply voltages for systems with signiﬁcant digital content as a power reduction tactic, it is natural to extend the design of the analog modulator to allow operation at quite low supply voltages.

The circuit block that presents a large design challenge at low supply voltages is the complementary CMOS switch of Figure 59.30. As the supply voltage approaches the sum of the n- and p-channel threshold voltages, there will be a range of signal voltages around the center of the supply range that will encounter large enough resistance through both switch devices. This effect tends to increase sampled signal distor- tion to objectionable levels.

In the complete modulator schematic of Figure 59.38, judicious choices of the various reference and common-mode voltage levels can be made to place them close to one or the other supply rail. This will allow the use of single polarity switch devices with low resistance. The exception to this, however, are the switches at the outputs of opamps. As can be seen in the simulation results in Section 59.2, the opamp output switches must handle signals which may cover almost the entire supply range in normal modulator operation.

To address this limitation, the switched opamp design technique has been developed [66,77]. Figure 59.47 shows a revision of the modulator of Figure 59.38 where the ﬁrst integrator opamp has been replaced by a switchable opamp. The clock line controlling the opamp determines when the ampliﬁer will function normally and when it will be placed in an inactive state where the signal current generated at the output terminals will be shut off. This essentially performs the function of the switches at the output of the ﬁrst opamp in Figure 59.38, but without requiring any analog switch block that is required to pass signals throughout the entire supply range.

An example switchable opamp design is shown in Figure 59.48 [68]. It is similar to the two-stage opamp of Figure 59.34, but includes clocked switch devices in the sources of M7 and M8. In addition, clocked switches are also inserted in series with the pole-splitting compensation capacitors. This freezes the state of charge on these capacitors while the opamp is in its inactive state so that the operating point may be quickly restored when returning to the active state.

An alternative approach to eliminating the need for full-range switches at the output of opamps is closing reset switches around the opamp to form a negative feedback loop in the inactive state [69].

Instead of switching off the opamp output current, this approach uses the gain properties of the opamp to clamp its output voltage in an inactive state. In some cases this approach can allow faster clock rates than the switched opamp approach.

Sampling Nonlinearity and Reference Corruption

The sigma-delta modulator is remarkably tolerant of most circuit nonidealities past the input sampling network. However, the linearity of the sampling process at the very ﬁrst input sampling capacitor will be the upper bound for the linearity of the entire modulator. Care must be exercised to ensure that the switches are sufﬁciently large so that the sampled voltage will be completely settled through their nonlinear resistance, but not so large so that any residual signal-dependent clock feedthrough is signiﬁcant.

Another susceptibility of modulators is to nonlinear corruption of the reference voltage. If the digital bit stream output, through a parasitic feedback path either on or off chip, can affect the reference voltage sampled during clock phase f2 in Figure 59.29, then there will be a term in the output signal dependent on the square of the input voltage. This will distort the noise-shaping properties of the modulator and generate second-harmonic distortion, even with fully differential circuitry. This is illustrated in the spectrum in Figure 59.49, which is the output of a modulator having the same conditions as Figure 59.14, except that a parasitic feedback path is assumed that would change the reference voltage by 1% for the “1” output bits on the previous cycle, relative to its value with “0” output bits. As can be seen by comparison with Figure 59.14, the ability of the modulator to shift quantization noise out of the baseband has been greatly compromised, and a prominent second harmonic has been generated. Care must be taken in chip and printed circuit board application design so that the reference voltage remains isolated from the signals carrying the output bit stream.

Fully differential circuitry is almost universally employed in integrated VLSI modulators to reduce sampling nonlinearity and reference contamination. Even-order nonlinearities and common-mode switch feedthrough are cancelled with fully differential circuits, and power supply rejection is greatly improved, leading to more isolated reference potentials. For high-precision modulators, the integrator topology is often changed from that of Figure 59.29 to Figure 59.50 [26,51]. The input signal and the DAC output voltage are sampled independently during phase f1, and then both discharged together into the summing node during f2. At the expense of additional area for capacitors and higher kT/C

noise, this arrangement insures that the same charge is drawn from the reference supply onto the DAC sampling capacitors CDP and CDM and then discharged into the summing node each cycle. Thus, a potential undesirable mechanism for reference supply loading that is dependent on the output bit history is eliminated [70].

High-Order Integrator Reset

Although careful design of the loop ﬁlter for higher-order modulators, as discussed in Section 59.3.1, will yield a generally stable design, their stability cannot be mathematically guaranteed as in the case of second-order loops. To protect against the highly undesirable state of low-frequency limit-cycle oscillations due to an occasional, but improbable, input overload condition, some form of forced integrator reset is sometimes used [26,51]. Generally these count the consecutive “1” or “0” bits out of the modulator, and close a resetting switch to discharge integration capacitors for a short time if the modulator generates a longer consecutive sequence than normal operation allows. This will naturally interrupt the operation of the modulator, but will only be triggered in the case of pathological input patterns for which linear operation would not necessarily be expected.

Another approach to a stability safety mechanism for higher-order loops is to arrange the scaling of the integrator gains so that they clip against their maximum output voltage swings in a prescribed sequence as the input level rises. The sequence is designed to gradually lower the effective order of the modulator [59], and return operation to a stable mechanism.

Multilevel Feedback

Expanding the second-order modulator to more than two-level feedback may be accomplished by the circuit in Figure 59.51. For K-level feedback, K - 1 latch comparators are arranged in a ﬂash structure as shown on the right. There must be a different offset voltage designed into each of the comparators so that they detect when each quantization level is crossed by the second integrator output. This can be implemented by a resistor string [54,71] or an input capacitive sampling network [72]. The output of the K - 1 comparators is then a thermometer code representation of the integrator output. This may be translated into binary for the modulator output, but the raw thermometer code is the most convenient to use as a set of feedback signals. They each will drive a switch that will select either VREF+ or VREF- to be used as the bottom plate potential for the integrator sampling capacitors. If all sampling capacitors are of equal value, the net charge being integrated will have a term that varies linearly with the

quantization level. Each comparator output drives two switches, so there are 2(K - 1) switches and capacitors in the sampling array.

In any practical integrated structure, even if careful common-centroid layout techniques are used, the precision with which the various capacitors forming the sampling array will be matched is typically limited to 0.1 or 0.2%. As discussed in Section 59.2.3, this will limit the harmonic distortion that is inherent in the modulator to about -60 dB or higher. However, by varying the assignment of which sampling switch is driven by which comparator output dynamically as the modulator is clocked, much of this distortion may be traded off for white or frequency-shaped noise at the modulator output. This technique is referred to as dynamic element matching.

One simple way of implementing dynamic element matching is indicated in Figure 59.51 with the block labeled “scrambler.” This block typically comprises an array of switches that provide a large number of permutations in the way the comparator output lines can be mapped onto sampling switch lines. A multitude of scrambler algorithms have been proposed in the literature. Some approaches attempt to randomize the mismatch errors, converting them into white noise [72,73]. Other approaches attempt to shape the mismatch error spectrum to achieve advantages similar to the way that a sigma-delta modulator shapes its quantization error. Some of these approaches are described below.

One conceptually simple approach for noise-shaping dynamic element matching is called individual level averaging [74,75]. As illustrated in Figure 59.52, separate counters (Rk) are maintained for each quantization level. When the kth quantization level is to be used, the counter Rk points to a cell in the capacitor array, and the next k cells are used to generate the quantizer output. The counter is then incremented by k using wrap-around arithmetic before the next sampling time. The individual level averaging algorithm insures that all of the capacitor cells are used equally when averaged over time. Furthermore, simulations and experimental data show that mismatch errors in the array are ﬁrst-order noise shaped such that much of the error energy appears outside the baseband and is suppressed by the decimation ﬁltering. The only real disadvantage of individual level averaging is that by requiring a separate counter for each quantization level, the implementation can become unwieldy as the number of quantization levels increases.

A simpliﬁcation of individual level averaging, called data-weighted averaging [76], is much less com- plex than individual level averaging for large or even modest numbers of quantization levels. As illustrated in Figure 59.53, a single pointer is used for all quantization values. Like individual level averaging, the pointer is updated after every sample such that all of the quantizer array cells are used equally, and the

mismatch errors are ﬁrst-order noise shaped. The disadvantage of data-weighted averaging is that, with only one pointer, data patterns can be created, which, in combination with array mismatch errors, can produce spectral tones.

A compromise in complexity between individual level averaging and data-weighted averaging is called grouped level averaging [77]. In grouped level averaging, the number of unit-cell pointers is more than one, but less than the number of quantization levels, as shown in Figure 59.54. The pointers are indexed such that no two adjacent quantization levels use the same pointer. If at least three pointers are used, simulations and experimental data show that the tone problems of data-weighted averaging are greatly diminished without the complexity penalties of individual level averaging.

Many other variations of dynamic element matching, too numerous to be catalogued here, have been published, ranging from complex algorithms that achieve better than ﬁrst-order noise shaping of the unit-cell mismatch errors to simple algorithms that simply whiten the mismatch noise spec- trum. Of particular note is a multiple stage butterﬂy network used to scramble the choice of array cells [78].

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