Oversampled Analog-to-Digital and Digital-to-Analog Converters:Circuit Building Blocks

Circuit Building Blocks

For analog-to-digital conversion, the modulator is implemented primarily in the analog domain as shown in Figure 59.16. In digital-to-analog conversion, the modulator output if ﬁltered by an analog reconstruc- tion ﬁlter as depicted in Figure 59.2. The basic analog circuit building blocks for these data converters are described in this section. These building blocks include switched-capacitor integrators, the ampliﬁers that are imbedded in the integrators, comparators, and circuits for sigma-delta based D/A conversion. At the end of this section, the techniques for continuous-time sigma-delta modulation are brieﬂy discussed.

Switched-Capacitor Integrators

Switched-capacitor integration stages are commonly used to perform the signal-processing functions of integration and summation required for realization of the discrete-time transfer functions A(z) and F(z) in Figure 59.16. The circuit techniques outlined herein are drawn from a rich literature of switched- capacitor ﬁlters [42–45] that is detailed elsewhere in this volume.

Figure 59.29 is a typical integrator stage for the case of single bit feedback [11,20], and is designed to perform the discrete-time computation

independent of the parasitic capacitances associated with the capacitive devices shown. The curved line in the capacitor symbol is the device terminal with which the preponderance of the parasitic capacitance is associated. For example, this will be the bottom plate of a stacked planar capacitance structure, where the parasitic capacitance is that between the bottom plate and the IC substrate. The circuit’s precision stems from the conservation of charge at the two input nodes of the operational ampliﬁer, and the cyclic return of the potential at those nodes to constant voltages. More details may be found in the Chapter 62, “Switched-Capacitor Filters.”

Fully differential circuits will be shown here, as these are almost universally preferred over single- ended circuits in monolithic implementations owing to their greatly improved power supply rejection, MOS switch feedthrough rejection, and suppression of even-order nonlinearities. The switches shown in Figure 59.29 are generally full CMOS switches, as detailed in Figure 59.30. However, integrators with very low-power supply voltages may necessitate the use of only one polarity of switch device, possibly with a switch gate voltage boosting arrangement [46]. Sampling capacitors CSP and CSM are designed with the same capacitance CS, and the effect of slight fabrication mismatches between the two will be mitigated by the common-mode rejection of the ampliﬁer. Similarly, integration capacitors CIP and CIM are designed to be identical with capacitance CI.

The discrete-time signal to be integrated is applied between the input terminals VIN+ and VIN-, and the output is taken between VOUT+ and VOUT-. VINCM is the common-mode input voltage required by the ampliﬁer. The single-bit DAC feedback voltage is applied between VDAC+ and VDAC-. The stage must be clocked by two nonoverlapping signals, f1 and f2. During the f1 phase, the differential input voltage is

sampled on the bottom plates of CSP and CSM, while their top plates are held at the ampliﬁer common- mode input level. During this phase, the ampliﬁer summing nodes are isolated from the capacitor network, and the ampliﬁer output will remain constant at its previously integrated value. During the f2 phase the bottom plates of the sampling capacitors CSP and CSM experience a differential potential shift of (VDAC - VIN), while the top plates are routed into the ampliﬁer summing nodes. By forcing its differ- ential input voltage to a small level, the ampliﬁer will effect a transfer of a charge of CS(VIN - VDAC) to the integration capacitors, and therefore the differential output voltage will shift to a new value by an increment of (CS/CI)(VIN - VDAC). Since this output voltage shift will accumulate from cycle to cycle, the discrete-time transfer function will be that of Eq. (59.33), with

Over several cycles of initial operation, the ampliﬁer input terminals will be driven to the common-mode level that is precharged onto the top plates of the sampling capacitors.

To suppress any signal-dependent clock feedthrough from the switches, it is helpful to slightly delay the clock phases that switch variable signal voltages with respect to the phases that switch current into constant potentials. The channel charge in each turned-on switch device can potentially dissipate onto the sampling capacitors when the switches are turned off, producing an error in the sampled charge. This channel charge is dependent on the difference between the switch gate to source voltage and its threshold voltage, and as the source voltage varies with signal voltage, the clock feedthrough charge will vary with the signal. By turning off the switches that see constant potentials at the end of each cycle ﬁrst, and thus ﬂoating the sampling capacitor, the only clock feedthrough is a charge that is to the ﬁrst-order independent of signal level, and results only in a common-mode shift that is suppressed by the ampliﬁer. This acts to reduce the nonlinearity of the integrator and the harmonic distortion generated by the modulator.

The timing for the delayed and undelayed clocks is illustrated in Figure 59.31, where the clock phases f1D and f2D represent phases that are slightly delayed versions of f1 and f2, respectively. The delayed clocks drive the switches that are subject to full signal voltage swings, the analog and reference voltage inputs, as shown in Figure 59.29. The undelayed clocks drive the switches associated with the ampliﬁer summing node and common-mode input bias voltage, which will always be driven to the same potential by the end of each clock cycle. A typical clock generator circuit to produce these phase relationships is shown in Figure 59.32. The delay time Dt is generated by the propagation delay through two CMOS inverters.

Other more complex, integration circuits are used in some sigma-delta implementations, for example, to suppress errors due to limited ampliﬁer gain [47,48] or to effectively double the sampling rate of the integrators [49,50]. For the modulator structures discussed in Section 59.3 that are more elaborate than

a second-order loop, more complex switched-capacitor ﬁltering is required. These may still, however, be designed with the same basic integrator architecture as in Figure 59.29, but with extra sampling capacitors feeding the ampliﬁer summing node to implement additional signal paths [26,33,51]. Consult the Chapter 62 in this volume on switched-capacitor ﬁltering for more information.

Operational Amplifiers

Embedded in the switched-capacitor integrator shown in Figure 59.29 is an operational ampliﬁer. There are three major types of operational ampliﬁers typically used in switched-capacitor integrators [52]: the folded cascode ampliﬁer [42], shown in Figure 59.33, the two-stage ampliﬁer [43], shown in Figure 59.34, and the class AB ampliﬁer [45], shown in Figure 59.35.

When the available supply voltage is high enough to permit stacking of cascode devices to develop high gain, a folded cascode ampliﬁer is commonly used. A typical topology is shown in Figure 59.33. The input devices are PMOS, since most IC processes feature PMOS devices that exhibit lower 1/f noise than their NMOS counterparts [53]. The input differential pair M1 and M2 is biased with the drain current of M3. FETs M5, M6, M11, and M12 function as current sources, and M7, M8, M9, and M10 form cascode devices that boost the output impedance. The ampliﬁer is compensated for stability in the integrator feedback loop by the dominant pole that is formed at its output node with the high output impedance and the load capacitance. In an integrator stage, the ampliﬁer will be loaded with the load capacitance of the following stage sampling capacitance as well as its own integration capacitance. The nondominant pole at the drains of M1 and M2 limit the unity-gain frequency, which can be quite high.

When the power supply voltage is limited, and cascode devices cannot be stacked and still preserve adequate signal swing, a two-stage ampliﬁer is a common alternative to the folded-cascode ampliﬁer. As shown in Figure 59.34, the input differential pair of M1 and M2 now feed the active load current sources of M9 and M10 to form the ﬁrst stage. The second stage comprises common-source ampliﬁers M7 and M8, loaded with current sources M5 and M6. Owing to the presence of two poles from the two stages of roughly comparable frequencies, compensation is generally achieved with a pole-splitting RC local feedback network

as shown [52]. Often the resistors RC1 and RC2 are actually implemented as NMOS devices biased into their ohmic region by tying their gates to VDD. In this arrangement the effective resistance of RC1 and RC2 will approximately track any drift in mobility of M7 and M8 over temperature and processing variations, preserving the compensated phase margin. For a given process, the bandwidth of a two-stage ampliﬁer is less than what can be achieved than by a folded cascode design, but because the two-stage ampliﬁer has no stacked cascode devices, the signal swing is higher.

In the case of modulators with higher clock speeds, both folded-cascode and two-stage ampliﬁers may have unacceptably long settling times; in these ampliﬁers, the maximum slewing current that can be applied to charge or discharge the load capacitance is limited by ﬁxed current sources. This slewing limitation can be overcome by a class AB ampliﬁer topology that can supply a variable amount of output current and is capable of providing a large pulse of current early in the settling cycle when the differential input error voltage is high. A typical class AB ampliﬁer topology is shown in Figure 59.35. The input differential pair from the folded-cascode and two-stage designs is replaced by M1 through M4, and their drain currents are mirrored to the output current sources M9–M12 by diode connected devices M5–M8. Cascode devices M13–M16 enhance the output impedance and gain. As with the folded cascode design, frequency compensation is accomplished by a dominant pole at the output node. The input voltage is fed directly to the NMOS input devices and to the PMOS input devices through the level shifting source follower and diode combination M17–M20. This establishes the quiescent bias current through the input network M1–M4, and therefore through the output devices as well.

In each of the three ampliﬁer topologies discussed above there is either one or a set of two matched current sources driving both differential outputs. These current sources are controlled by a gate bias line labeled VCMBIAS. The current output of these devices will determine the common-mode output voltage of the ampliﬁer independent, to the ﬁrst order, of the ampliﬁed differential signal. The appropriate potential for VCMBIAS is determined by a feedback loop that is only operable in the common mode and is separate from the differential feedback instrumental in the charge integration process.

Since a discrete-time modulator is, by its nature, clocked periodically, a natural choice for the imple- mentation of this common-mode feedback loop is the switched capacitor network of Figure 59.36 [44,45]. Capacitors CCM1 and CCM2 act as a voltage divider for transient voltages that derives the average, or common mode, voltage of the ampliﬁer output terminals. This applies corrective negative feedback transients to the VCMBIAS node to stabilize the feedback loop during each clock period while the ampliﬁer is differentially settling.

A DC bias is then maintained on CCM1 and CCM2 by the switched capacitor network on the left side of the ﬁgure. This will slowly transfer the charge necessary to establish and maintain a DC level shift that makes up the difference between the common-mode level desired at the ampliﬁer output terminals

(VCMDES) and the approximate gate bias required by the common-mode current devices (VBAPPROX). The former is usually set at mid supply by a voltage divider, and the latter can be derived from a matched diode-connected device. Since the clocking of this switching network is done synchronously to the ampliﬁer integrator clocking, no charge injection will occur during the sensitive settling process of the ampliﬁer. To minimize the charge injection at the clock transitions, capacitors CS1 and CS2 are usually made very small, and therefore dozens of clock cycles may be required for the common-mode bias to settle and the modulator to become operable.

Comparators

The noise-shaping mechanism of the modulator feedback loop allows the loop behavior to be tolerant of large errors in circuit behavior at locations closer to the output end of the network. Modulators are generously tolerant of large offset errors in the comparators used in the A/D converter forming the feedback path. For this reason, almost all modulators use simple regenerative latches as comparators. No preamp is generally needed, as the small error from clock kickback can easily be tolerated. Simulations show that offset errors that are even as large as 10% of the reference level will not degrade modulator performance signiﬁcantly.

The circuit of Figure 59.37 is typical [54]. This is essentially a latch composed of two cross-connected CMOS inverters, M1–M4. Switch devices M5–M8 will disconnect this network when the clock input is low, and throw the network into a regenerative mode with the rising edge of the clock. The state in which the regeneration will settle may be steered by the relative strengths of the bias current output by devices M9 and M10, which in turn depend on the differential input voltage.

Complete Modulator

Figure 59.38 illustrates a complete second-order, single bit feedback modulator assembled from the components discussed above [11]. The discrete-time integrator gain factors that are derived in Sections 59.2 and 59.3 are realized by appropriate ratios between the integration and sampling capacitors in each stage. Since the single bit feedback DAC is only responsible for generating two output levels, it may be implemented by simply switching an applied differential reference voltage VREF+ to VREF- in a direct or reversed sense to the sampling capacitor bottom plates during the ampliﬁer integration phase, f2.

D/A Circuits

For the D/A converter system shown in Figure 59.2, the oversampled bit stream is generated by straight- forward digital implementations of the modulator signal ﬂow graphs discussed in Section 59.2. The remaining analog components are the low-resolution DAC block and the reconstruction ﬁlter. Integrated sigma-delta D/A implementations are often employ two-level quantization, and the DAC block may

either be designed as charge-based [55] or current-based [56]. Multilevel DAC approaches are also used, but for harmonic content less than about 60 dB below the reference some form of dynamic element matching must be added, as discussed in Section 59.6.7.

The charge-based approach for sigma-delta D/A conversion is illustrated in Figure 59.39, which is similar to the switched capacitor integrator of Figure 59.29, but without an analog signal input. As in

Figure 59.38, VDAC may be either polarity of VREF according to the bit value to be converted. Figure 59.40 shows a typical topology for current-based converters. In both cases the leaky integration function around the ampliﬁer contributes to the ﬁrst pole of the reconstruction ﬁltering. An efﬁcient combination of the current-based approach and a digital delay line realizing an FIR reconstruction ﬁlter is also possible [57]. Additional reconstruction ﬁltering beyond that provided by in the DAC may also be necessary. This is accomplished using the appropriate analog sampled-data ﬁltering techniques described in

Chapter 62.

Continuous-Time Modulators

In general, the ampliﬁers contained in the switched-capacitor integrators in a sampled-data sigma-delta data converter dissipate the majority of the analog circuit power. Since the integrator sections must settle accurately within each clock period at the oversampled rate, the ampliﬁers must often be designed with

a unity-gain frequency much higher than the oversampled rate; typical unity-gain frequencies are in hundreds of MHz.

In applications in which dissipating the lowest possible power is important, sigma-delta modulators may also be implemented using continuous-time integrators. In these continuous-time modulators, the analog signal is not sampled until the quantizer at the back of the modulator loop [58]. Owing to the typical means employed for the DAC feedback, continuous-time modulators tend to be more sensitive to sampling clock jitter, but the inﬂuences of any aliasing distortion and nonlinearity at the sampler take place late in the loop where noise shaping is steepest, and as a consequence the anti-aliasing ﬁlter of Figure 59.1 may often be omitted [59]. The power advantage comes from the relaxed speed requirement of the integrator stages, which now need only have unity gain frequencies on the order of the oversampled clock frequency.

Instead of switched-capacitor discrete-time integrators, the continuous-time modulators generally use active Gm-C integrators. Circuits like the one shown in Figure 59.41 are typical [59]. The input differential pair M1 and M2 is degenerated by source resistance R1 to improve linearity. The output analog voltage is developed across capacitor C1, which may be split as shown to place the bottom plate parasitic capacitance at a common-mode node. As the integrator is now unclocked, continuous-time common- mode feedback must be used, as discussed in the literature for continuous-time ﬁltering [60].

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