Nyquist-Rate ADC and DAC:ADC Architectures

ADC Architectures

In general, the main criteria of choosing ADC architectures are resolution and speed, but auxiliary requirements such as power, chip area, supply voltage, latency, operating environment, or technology often limit the choices. The current trend is toward low-cost integration without using expensive discrete technologies such as thin ﬁlm and laser trimming. Therefore, a growing number of ADCs are being implemented using mainstream VLSI technologies such as CMOS or BiCMOS.

Slope-Type ADC

Traditionally, slope-type ADCs have been used for multimeters or digital panel meters mainly because of their simplicity and inherent high linearity. There can be many variations, but dual- or triple-slope techniques are commonly used because the single-slope method is sensitive to the switching error. The resolution of this type of ADC depends on the accurate control of charge on the capacitor. The dual-slope technique in Figure 58.6(a) starts with the initialization of the integrating capacitor by opening the switch S1 with the input switch S2 connected to Vref. If Vref is negative, Vx will increase linearly with a slope of –Vref /RC. After a time T1, the switch S2 is switched to Vin. Then, Vx will decrease with a new slope of –Vin /RC. The comparator detects the zero-crossing time T2. From T1 and T2, the digital ratio of Vin /Vref can be obtained as T1/T2. The triple-slope technique shown in Figure 58.6(b) needs no op-amp to reduce the offset effect. Unlike the dual-slope method comparing two slopes, it measures three times T1, T2, and T3 by charging the capacitor with Vref, Vin, and ground with three switches S1, S2, and S3, respectively. The comparator threshold can be set to negative VTH. From three time measurements, the ratio of Vin /Vref can be computed as (T2 – T3)/(T1 – T3).

Successive-Approximation ADC

The simplest concept of A/D conversion is comparing analog input voltage with an output of a DAC. The comparator output is fed back through the DAC as explained in Figure 58.7. The successive-approximation register (SAR) performs the most straightforward binary comparison. The sampled input is compared with

the DAC output by progressively dividing the range by two as explained in the 4-b example. The conversion starts by sampling input, and the ﬁrst MSB decision is made by comparing the sample-and-hold (S/H) output with Vref /2 by setting the MSB of the DAC to 1. If the input is higher, the MSB stays as 1. Otherwise, it is reset to 0. In the second bit decision, the input is compared with 3Vref /4 in this example by setting the second bit to 1. Note that the previous decision set the MSB to 1. If the input is lower, as in the example shown, the second bit is set to 0, and the third bit decision is done by comparing the input with 5Vref /

8. This comparison continues until all the bits are decided. Therefore, the N-bit successive-approxi-

mation ADC requires N+1 clock cycles to complete one sample conversion.

The performance of the successive-approximation ADC is limited by the DAC resolution and the comparator accuracy. The commonly used DACs for this architecture are a resistor-string DAC and a capacitor-array DAC. Although binary-weighted capacitors have a 10b-level matching in MOS [1], diffused resistors have poor matching and high voltage coefﬁcient. If differential resistor-string DACs are used, performance can be improved to the capacitor-array DAC level [2]. In general, the capacitor DAC exhibits poor DNL while the resistor-string DAC exhibits poor INL.

Flash ADC

The most straightforward way of making an ADC is to compare the input with all the divided levels of the reference simultaneously. Such a converter is called a ﬂash ADC, and the conversion occurs in one step. The ﬂash ADC is the fastest among all ADCs. The ﬂash ADC concept is explained in Figure 58.8, where divided reference voltages are compared to the input. The binary encoder is needed because the output of the comparator bank is thermometer-coded. The resolution is limited both by the accuracy of the divided reference voltages and by the comparator resolution. The metastability of the comparator produces a sparkle noise when the comparator is indecisive. The reference division can be done using capacitor dividers [3,4] or transistor sizing [5] for small-scale ﬂash ADCs. However, only resistor-string DACs can provide references as the number of bits grows.

In practical implementations, the limit is the exponential growth in the number of comparators and resistors. For example, an N-bit ﬂash needs 2N – 1 comparators and 2N resistors. Furthermore, for the Nyquist-rate sampling, the input needs a S/H to freeze the input for comparison. As the number of bits grows, the comparator bank presents a signiﬁcant loading to the input S/H, diminishing the speed advantage of this architecture. Also, the control of the reference divider accuracy and the comparator resolution degrades, and the power consumption becomes prohibitively high. As a result, ﬂash converters with more than 10-b resolution are rare. Flash ADCs are commonly used as coarse quantizers in the pipeline or multi-step ADCs. The folding/interpolation ADC, which is conceptually a derivative of the ﬂash ADC, reduces the number of comparators by folding the input range [6].

For high resolution, the ﬂash ADC needs a low-offset comparator with high gain, and the comparator is often implemented in a multi-stage conﬁguration with offset cancelation. The front-end of the multistage comparator is called a preampliﬁer. A technique called interpolation saves the number of preampliﬁers by interpolating the adjacent preampliﬁer outputs as shown in Figure 58.9(a), where two preampliﬁer

outputs Va and Vb are used to generate three more outputs V1, V2, and V3 using a resistor divider. The interpolation can improve the DNL within the interpolated range, but the overall DNL and INL are not improved. Interpolating any arbitrary number of levels is possible by making more resistor taps. The interpolation is usually done using resistors, but it is also possible to interpolate using capacitors and current sources. However, interpolating with independent current sources does not improve the DNL.

Another technique called averaging, as explained in Figure 58.9(b) is often used to average out the offsets of the neighboring preampliﬁers as well as to enhance the accuracy of the reference divider [7]. The idea is to couple the outputs of the preampliﬁer transconductance (Gm) stage so that the offset errors can be spread over the adjacent preampliﬁer outputs as explained. For example, if the coupling resistor value is inﬁnite, there exists no averaging. As the coupling resistor value decreases, one preampliﬁer output becomes the weighted sum of the outputs of its neighboring preampliﬁers. Therefore, the overall DNL and INL can improve signiﬁcantly [8]. However, for the case in which errors to average have the same polarity, the averaging is not that effective. In practice, both the interpolation and the averaging concepts are often combined.

Subranging ADC

Although the interpolation and averaging techniques simplify the ﬂash ADC, the number of comparators stays the same. Instead of making all the bit decisions at once, resolving a few bits at a time makes the system simpler and more manageable. It also enables us to use a digital error correction concept. The simplest subranging ADC concept is explained in Figure 58.10 for the two-step conversion case. It is a straightforward subranging since one subrange out of 2M subranges is chosen in the coarse M-bit decision. Once one subrange is selected, the N-bit ﬁne decision can be made using a ﬁne reference ladder inter- polating the selected subrange.

Note that the subrange after the coarse decision is Vref /2M and the ﬁne comparators should have a resolution of M + N bits. Unless the digital error correction with redundancy is used, the coarse comparators should also have a resolution of M + N bits.

Multi-Step ADC

The tactic of making a few bit decisions at a time as shown in the subranging case can be generalized. A slight modiﬁcation of the subranging architecture shown in Figure 58.11(a) to include a residue

ampliﬁer with a gain of 2M results in Figure 58.11(b). The residue is deﬁned as the difference between the input and the nearest DAC output lower than the input. The difference between the two concepts is subtle, but including one residue ampliﬁer drastically changes the system requirements. The obvious advantage of using the residue ampliﬁer is that the ﬁne comparators do not need to be accurate because the residue from the coarse decision is ampliﬁed by 2M. That is, the subrange after the coarse decision is no longer Vref /2M. The disadvantage is the accuracy and settling of the high-gain residue ampliﬁer.

Whether the residue is ampliﬁed or not, the subranging block consists of a coarse ADC, a DAC, a residue subtractor, and an ampliﬁer. In theory, this block can be repeated as shown in Figure 58.12. How many times it is repeated determines the number of steps. So, in general terms, the n-step ADC

has n–1 subranging blocks. To complete a conversion in one cycle, usually poly-phase subdivided clocks are needed. Due to the difﬁculty in clocking, the number of steps for the multi-step architecture is usually limited to two, which does not incur a speed penalty and needs the standard two-phase clocking.

There are many variations in the multi-step architecture. If no ploy-phase clocking is used, it is called a ripple ADC. Also in the two-step ADC, if one ADC is repeatedly used both for the coarse and ﬁne decisions, it is called a recycling ADC [9]. In this ADC example, the capacitor-array multiplying DAC (MDAC) also performs the S/H function in addition to the residue ampliﬁcation. This MDAC, with either a binary-ratioed or thermometer-coded capacitor array, is a general form of the residue ampliﬁer. The same capacitor array has been used with a comparator to implement a charge-redistribution successive-approximation ADC [1]. This MDAC is suited for MOS technologies, but other forms of the residue ampliﬁcation are possible using resistor-strings or current DACs.

Pipeline ADC

The complexity of the two-step ADC, although manageable and simpler than the ﬂash ADC, still grows exponentially as the number of bits to resolve increases. Speciﬁcally, for high resolution above 12 b, the complexity reaches about the maximum, and a need to pipeline subranging blocks arises. The pipeline ADC architecture shown in Figure 58.13 is the same as the subranging or multi-step ADC architecture shown in Figure 58.12 except for the interstage S/H. Since the S/Hs are clocked by alternating clock phases, each stage needs to perform the decision and the residue ampliﬁcation in each clock phase. Pipelining the residue greatly simpliﬁes the ADC architecture. The complexity grows only linearly with the number of bits to resolve. Due to its simplicity, the pipeline ADCs have been gaining popularity in the digital VLSI environment.

In the pipeline ADC, each stage resolves a few bits quickly and transfers the residue to the following stage so that the residue can be resolved further in the subsequent stages. Therefore, the accuracy of the interstage residue ampliﬁer limits the overall performance. The following four non-ideal error sources can affect the performance of the multi-step or pipeline ADCs: ADC resolution, DAC resolution, gain error of the residue ampliﬁer, and inaccurate settling of the residue ampliﬁer. The offset of the residue ampliﬁer does not affect the linearity, but it appears as a system offset. Among these four error sources, the ﬁrst three are static, but the residue ampliﬁer settling is dynamic. If the residue ampliﬁer is assumed to settle within one clock phase, three static error sources are limiting the linearity performance.

Figure 58.14 explains the residue from the 2-b stage in the systems shown in Figures 58.12 and 58.13. In the ideal case, as the input is swept from 0 to the full range Vref , the residue change from 0 to Vref repeats each time Vref is subtracted at the ideal locations of the 2-b ADC thresholds, which are Vref/4 apart. In this case, the 2-b stage does not introduce any nonlinearity error. However, in the other cases

with ADC, DAC, and gain errors, the residue ranges do not match with the ideal full-scale Vref. If the residue range is smaller than the full range, missing codes are generated; and if the residue goes out of bounds, excessive codes are generated at the ADC thresholds. Unlike the DAC and gain errors, the ADC error appears as a shift of residue by Vref as long as the DAC and the residue ampliﬁer are ideal. This implies that the ADC error can be corrected digitally by restoring the ideal range of Vref.

Digital Error Correction

Any multi-step or pipeline ADC system can be made insensitive to the ADC error if the ADC error is digitally corrected. The out-of-range residue can still be digitized by the following stage if the residue ampliﬁer gain is reduced. That is, if the residue ampliﬁer gain is set to 2N–1 instead of 2N, the residue plots are as shown in Figure 58.15. If the residue is bounded with the full range of 0 to Vref, the inner range from Vref /4 to 3Vref /4 is the normal conversion range, and two redundant outer ranges are used to cover the residue error resulting from the inaccurate coarse conversion. This redundancy requires extra resolution to cover the overrange. The half ranges on both sides are used to cover the residue error in this 2-b case. That is, one full bit of extra resolution is necessary for redundancy in the 2-b case. However, the amount of redundancy depends on the ADC error range to be corrected in the multi-bit cases [10]. In general, it is a tradeoff between comparator resolution and redundancy.

The range marked as B is the normal range, and A and C indicate the correction ranges in Figure 58.15(b). The digital correction is to overlap one digital bit when adding digital numbers from the pipelined stages. Since the residue errors occur only at the comparator thresholds, shifting the comparator thresholds by half LSB has an advantage of saving one comparator. Figure 58.16 compares the residue plots for two cases with and without the ADC threshold shift by Vref /8. This is to fully utilize the ADC conversion range from 0 to Vref. The shift of Vref /8 makes the residue start from 0 and end at Vref in Figure 58.16(b), contrary to the previous case where the residue starts from Vref /4 and ends at 3Vref /4. This results in saving one comparator. The former case needs 2N–1 comparators, while the latter case needs 2N–2.

Digital correction in the half-bit-shifted case is explained in the 4-b ADC example, made of three stages using one-bit correction per stage in Figure 58.17. The vertical axis marks the signal and residue levels as well as ADC decision levels. The dotted and shaded areas follow the residue paths when the ADC error occurs, but the end results are the same after digital correction. This half interval shift is valid for stages resolving any number of bits. Overall, the digital error correction enables fast data conversion using inaccurate comparators. However, the DAC resolution and the residue gain error still remain as the fundamental limits in multi-step and pipeline ADCs. The currently known ways to overcome these limits are either trimming or self-calibration.

One-Bit per Stage Pipeline ADC

The degenerate case of the pipeline ADC is when only one bit is resolved per stage as shown in Figure 58.18. Each stage multiplies its input Vin by two and subtracts the reference voltage Vref to generate the residue voltage. If the sign of 2Vin – Vref is positive, the bit is 1 and the residue goes to the next stage. Otherwise, the bit is 0 and Vref is added back to the residue before it goes to the next stage. However, in reality, it is more desirable if the reference restoring time is saved. In the non-restoring algorithm, the previous bit decision affects the polarity of the reference voltage to be used in the current bit decision. If the previous bit is 1, the residue voltage is 2Vin – Vref, as in the restoring algorithm. But if the previous bit is 0, the residue voltage is 2Vin + Vref.

The switched-capacitor implementation of the basic functional block performing 2Vin ± Vref is explained using two identical capacitors and one op-amp in Figure 58.19. During the sampling phase, the bottom plates of two capacitors are switched to the input, and the top plate is connected either to

the op-amp output or to the op-amp input common-mode voltage. During the ampliﬁcation phase, one of the capacitors is connected to the output of the op-amp for feedback, but the other is connected to ±Vref . Then, the output of the op-amp will be 2Vin – Vref and 2Vin + Vref , respectively, after the op-amp settles.

However, this simple one-bit pipeline ADC is of no use if the comparator resolution is limited. If any redundancy is used for digital correction, at least two bits should be resolved. A close look at Figure 58.16(b) gives a clue to using the simple functional block shown in Figure 58.19 for the 2-b residue ampliﬁcation. The case explained in Figure 58.16(b) is sometimes called 1.5-b rather than 2-b because it needs only

three DAC levels rather than four. The functional block in Figure 58.19 can have a two-level DAC subtracting ±Vref . However, in differential architecture, by shorting the input, one midpoint can be interpolated. Using the tri-level DAC, the 1.5-b per stage pipeline ADC can be implemented with the following algorithm [12]. If the input Vin is lower than –Vref /4, the residue output is 2Vin + Vref . If the input is higher than Vref /4, the residue output is 2Vin – Vref . If the input is in the middle, the output is 2Vin.

Algorithmic, Cyclic, or Recursive ADC

The interstage S/H used in the multi-step architecture provides a ﬂexibility of the pipeline architecture. In the pipeline structure, the same hardware repeats as shown in Figure 58.13. That is, the throughput rate of the pipeline is fast while the overall latency is limited by the number of stages. Instead of repeating the hardware, using the same stage repeatedly greatly saves hardware, as shown in Figure 58.20. That is, the throughput rate of the pipeline is directly traded for hardware simplicity. Such a converter is called an algorithmic, cyclic, or recursive ADC. The functional blocks used for the algorithmic ADC are identical to the ones used in the pipeline ADC.

Time-Interleaved Parallel ADC

The algorithmic ADC just described sacriﬁces the throughput rate for small hardware. However, the time-interleaved parallel ADC takes quite the opposite direction. It duplicates more hardware in parallel for higher throughput rates. The system is shown in Figure 58.21, where the throughput rate increases by the number of parallel paths multiplexed. Although it signiﬁcantly improves the throughput rate and many reﬁnements have been reported, it suffers from many problems [13]. Due to the multiplexing, even static nonlinearity mismatch between paths appears as a ﬁxed pattern noise. Also, it is difﬁcult to generate clocks with exact delays, and inaccurate clocking increases the noise ﬂoor.

Folding ADC

The folding ADC is similar to the ﬂash ADC except for using fewer comparators. This reduction in the number of comparators is achieved by replacing the comparator preampliﬁers with folding ampliﬁers. In its original arrangements [14], the folding ADC digitizes the folded signal with a ﬂash ADC. The folded signal is equivalent in concept to the residue of the subranging, multi-step, or pipeline ADC, but the difference is that the generation of the folding signal is done solely in the analog domain. Since the digitized code from the folding ampliﬁer output repeats over the whole input range, a coarse coding is required, as in all subranging-type ADCs.

Consider a system conﬁgured as a 4-b folding ADC as shown in Figure 58.22. Four folding ampliﬁers can be placed in parallel to produce four folded signals. Comparators check the outputs of the folding ampliﬁers for zero crossing. If the input is swept, the outputs of the ﬁne comparators show a repeating pattern, and eight different codes can be obtained by the four comparators. Because there are two identical ﬁne code patterns, one comparator is needed to distinguish them. However, if this coarse comparator is misaligned with the ﬁne quantizer, missing codes will result. A digital correction similar to that for the multi-step or pipeline ADC can be employed to correct the coarse quantizer error. For this system example, one-bit redundancy is used by adding two extra comparators in the coarse quantizer. The shaded region in the ﬁgure is where errors occur.

Having several folded signals instead of one has many advantages in designing high-speed ADCs. The folding ampliﬁer requires neither linear output nor accurate settling. This is because in the folding ADC, the zero-crossings of the folded signals matter, but not their absolute values. Therefore, the offset of the folding ampliﬁers becomes the most important design issue. The resolution of the folding ADC can be further improved using the interpolation concept. When the adjacent folded signals are interpolated by I times, the number of zero-crossing points are also increased by I times. So, the resolution of the ﬁnal ADC is improved by log2I bits. The higher bound for the degree of interpolation is set by the comparator resolution, the gain of the folding ampliﬁers, the linearity of folded signals, and the interpolation accuracy. Since the folding process increases the internal signal bandwidth by the number of foldings, the folding ADC performance is limited by the folding ampliﬁer bandwidth. To increase the number of foldings while maintaining the reasonable comparator resolution, the folding ampliﬁer’s gain should be high. Since the higher gain limits the ampliﬁer bandwidth, it is necessary to cascade the folding stages [6,8].

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