Low-Power Memory Circuits:Flash Memory

Flash Memory

In recent years, flash memories have become one of the fastest growing segments of semiconductor memories [13,14]. Flash memories are used in a broad range of applications, such as modems, networking equipment, PC BIOS, disk drives, digital cameras, and various new microcontrollers for leading edge embedded applications. They are primarily used for permanent mass data storage. With a rapidly emerging area of portable computing and mobile telecommunications, the demand for low-power, low-voltage flash memories increases. Under such conditions, flash memories have to employ low-power tunneling mech- anisms for both write and erase operation, thinner tunneling dielectrics, and on-chip voltage pumps.

Low-Power Circuit Techniques for Flash Memories

To prolong the battery life in mobile devices, significant reductions of power consumption in all electronic components have to be achieved. One of the fundamental and most effective methods is a reduction of a power supply voltage. This method has been observed also in flash memories. Designs with a lower 3.3 V power supply as opposed to a traditional 5 V have been reported [19–24]. In addition, multilevel architectures that lower the cost per bit, increase memory density and improve energy efficiency per bit have emerged [21,24]. Kawahara et al. [26] and Otsuka and Horowitz [27] have identified major bottle- necks when designing flash memories for low-power, low-voltage operation and proposed suitable tech- nologies and techniques for deep submicron sub-2 V power supply flash memory design. Owing to its construction, a flash memory requires high-voltage levels for program and erase operations often exceed- ing 10 V (Vpp). The core circuitry that operates at these voltage levels cannot be aggressively scaled as the peripheral circuitry that operates with standard Vdd. Peripheral devices are designed to improve the power and performance of the chip, whereas core devices are designed to improve the read performance. Parameters, such as the channel length, the oxide thickness, the threshold voltage, and the breakdown voltage have to be adjusted to withstand high voltages. Technologies that allow two different transistor environments on the same substrate have to be used. An example of transistor parameters in a multi- transistor process is given in Table 57.2.

Technologies reaching deep submicron levels, 0.25 µm and lower, can experience three major problems (summarized in Figure 57.12): (1) layout of the peripheral circuits due to a scaled flash memory cell; and

(1) an accurate voltage generation for the memory cells to provide the required threshold voltage and narrow deviation; and (3) deviations in dielectric film characteristics caused by large number of memory cells. Kawahara et al. [26] have proposed several circuit enhancements that address these problems. They proposed a sensing circuit with a relaxed layout pitch, BL clamped sensing multiplex, and intermittent burst data transfer for a three times feature-size pitch. They also proposed a low-power dynamic bandgap generator with voltage boosted by using a triple-well bipolar transistors and a voltage-doubler charge pumping, for accurate generation of 10–20 V that operate at Vdd under 2.5 V. They demonstrated these improvements on a 128-Mb experimental chip fabricated using 0.25 µm technology.

On a circuit level, three problems have been identified by Otsuka and Horowitz [27]: (1) interface between peripheral and core circuitry; (2) sense circuitry and operation margin; and (3) internal high- voltage generation.

During program and erase modes, the core circuits are driven with higher voltage than the peripheral circuits. This voltage is higher than Vdd to achieve good read performance. Therefore, a level shifter circuit is necessary to interface between the peripheral and core circuitry. However, when a standard power supply (Vdd) is scaled to 1.5 V and lower, the threshold voltage of Vpp transistors will become comparable to one half of Vdd or less, which results in significant delay and poor operation margin of the level shifter and, consequently, degrades the read performance. A level shifter is necessary for the row decoder, column selection, and source selection circuit. Since the inputs to the level shifters switch while Vpp is at the read Vpp level, the performance of the level shifter needs to be optimized only for a read operation. In addition to a standard erase scheme, flash memories utilizing a negative-gate erase or program scheme have been reported [19,23]. These schemes utilize a single voltage supply which results in lower power consumption. The level shifters in these flash memories have to shift a signal from Vdd to Vpp and from GND to Vbb. Conventional level shifters suffer from delay degradation and increased power consumption when driven with low power supply voltage. There are several reasons attributed to these effects. First, at low Vdd (1.5 V) the threshold voltage of Vpp transistors is close to half of power supply voltage which results in an insufficient gate swing to drive the pull-down transistors (see Figure 57.13). This also reduces the operation margin of these shifters for the threshold voltage fluctuation of the Vpp transistor. Second, a rapid increase in power

consumption at Vdd under 1.5 V is due to DC current leakage through Vpp to GND during the transient switching. At 1.5 V, 28% of the total power consumption of Vpp is due to DC current leakage. Two signal shifting schemes have been proposed, one for a standard flash memory and another for a negative-gate erase or program flash memories. The first proposed design is shown in Figure 57.14. This high-level shifter uses a bootstrapping switch to overcome the degradation due to a low input gate swing and improves the current drivability of both pull-down drivers. It also improves the switching delay and the power consumption at 1.5 V, because the bootstrapping reduces the DC current leakage during the transient switching. Consequently, the bootstrapping technique increases the operation margin. The layout overhead from the boot- strapping circuit, capacitors, and an isolated n-well is negligible compared with the total chip area because it is used only as the interface between the peripheral circuitry and the core circuitry. Figure 57.15 shows the operation of the proposed high-level shifter and Figure 57.16 illustrates the switching delay and the power consumption versus the power supply voltage of the conventional design and the proposed design. The second proposed design, shown in Figure 57.17, is a high-/low-level shifter that also utilizes a boot- strapping mechanism to improve the switching speed, reduce DC current leakage and improve operation margin. The operation of the proposed shifter is illustrated in Figure 57.18. At 1.5 V, the power consumption decreases by 40% compared with a conventional two-stage high-/low-level shifter (see Figure 57.19). The proposed level shifter does not require an isolated n-well and therefore the circuit is suitable for a tight- pitch design and a conventional well layout.

In addition to the more efficient level-shift scheme, Otsuka and Horowitz [27] also addressed the problem of sensing under very low power supply voltages (≤1.5 V) and proposed a new self-bias BL-sensing method that reduces the delay’s dependence on BL capacitance and achieves 19 ns reduction of the sense delay at low voltages. This enhances the power efficiency of the chip. On a system level,

Tanzawa et al. [29] proposed an on-chip error correcting circuit (ECC) with only 2% layout overhead. By moving the ECC from off-chip to on-chip, 522-byte temporary buffers that are required for conventional ECC and occupy a large part of ECC area, have been eliminated. As a result, the area of ECC circuit has been reduced by a factor of 25. The on-chip ECC has been optimized which resulted in an improved power efficiency by a factor of 2.