Low-Power Memory Circuits:Ferroelectric Memory

Ferroelectric Memory

Ferroelectric memory (FeRAM) combines the advantages of a nonvolatile flash memory and the density and speed of a dynamic random-access memory (DRAM) memory. Advances in low-voltage, low-power design toward mobile computing applications have been seen in the literature [40,41]. Hirano et al. [40] reported a new 1-transistor 1-capacitor nonvolatile ferroelectric memory architecture that operates at 2 V with 100 ns access time. They achieved these results by using two new improvements, a BL-driven

read scheme and a nonrelaxation reference cell. In previous ferroelectric architectures, either a cell plate- driven or noncell plate-driven read scheme (Figure 57.26[a] and Figure 57.26[b]) was used [42,43]. Eventhough, the first architecture could operate at low supply voltages, the large capacitance of the cell plate, which connects to many ferroelectric capacitors and a large parasitic capacitor, would degrade the performance of the read operation due to large transient time necessary to drive the cell plate. The second architecture suffers from two problems. The first problem is a risk of losing the data stored in the memory due to the leakage current of a capacitor’s storage node. The storage node of a memory cell is floating and the parasitic p–n junction between the storage node and the substrate leaks the current. Consequently, the storage node reaches the Vss level and another node of the capacitor is kept at 1/2Vdd which causes the data destruction. Therefore, this scheme requires a refresh operation of a memory cell data.

The second problem arises from a low-voltage operation. Owing to a voltage across the memory cell capacitor being at 1/2Vdd under this scheme, the supply voltage must be twice as high as the coercive voltage of ferroelectric capacitors which prevents the low-voltage operation. To overcome these problems, Hirano et al. [40] have developed new BL-driven read scheme which is shown in Figure 57.27 and Figure 57.28. The BL-driven circuit precharges the BLs to supply Vdd voltage. The cell plateline is fixed at ground voltage in the read operation. An important characteristic of this configuration is that the BLs are driven while the cell plate is not driven. Also, the precharged voltage level of the BLs is higher than that of the cell plate. Figure 57.29 shows the limitations of previous schemes and the new scheme. During the read operation, the first previously presented scheme [42] requires a long delay time to drive the cell plateline (PL). However, the proposed scheme exhibits faster transient response because

the BL capacitance is less than 1/100 of the cell plateline capacitance. The second previously presented scheme [43] requires a data refresh operation to secure data retention.

The read scheme proposed by Hirano et al. [40] does not require any refresh operation since the cell plate voltage is at 0 V during the standby mode.

The reference voltage generated by a reference cell is a critical aspect of a low-voltage operation of ferroelectric memory. The reference cell is constructed with one transistor and one ferroelectric capacitor. While a voltage is applied to the memory cell to read the data, the BL voltage reading from the reference cell is set to about the midpoint of “H” and “L,” which are read from the main-memory-cell data. The state of the reference cell is set to “Ref ” (left side of Figure 57.30). However, a ferroelectric capacitor suffers from the relaxation effect which decreases the polarization (right side of Figure 57.30). As a result, each state of the main memory cells and the reference cell is shifted and the read operation of “H” data is marginal and prohibits the scaling of power supply voltage. Hirano et al. [40] have developed a reference cell that does not suffer from a relaxation effect, moves always along the curve from the “Ref ” point and therefore enlarges the read operation margin for “H” data. This proposed scheme enables a low-voltage operation down to 1.4 V. Hirano et al. [48] successfully developed a low-power embedded 1 Mbit FeRAM operating down to 1.5 V with a ferroelectric capacitor operating down to 0.75 V. The group used two new techniques: a nondriven plate scheme with a nonrefresh operation and a selected driven BL scheme. The combined effect of these two schemes is significant. The memory size is reduced by 53% and the power consumption by 98%. The first scheme uses a reset circuit to reset storage nodes of the memory cells to the voltage of the PL, which isolates the storage nodes of the memory cells. As seen in Figure 57.31, the voltage of the PL and the reset node (VRST) is set to Vdd/2 (0.75 V). The second scheme is based on (a) a column select-driven BL and (b) divided BL concepts. The BL with a selectable memory cell is fully amplified until the power supply voltage and the other BLs reach 0.5Vdd. The operation is shown in Figure 57.32.

The same group lead by Yamaoka et al. [49] achieved a very low-voltage operation using a novel reference voltage scheme and a multilayer shielded BL structure. The one-transistor one-capacitor (1T1C)-embedded memory operates at just 0.9 V. The new scheme overcomes three problems: first, reference voltage shift by imprint; second, wide distribution of the reference voltage; and third, read margin reduction due to the noise between the BLs in the high-density memory. The proposed reference scheme is shown in Figure 57.33. In the first phase, the stored Data H and L are transferred during read operation to CBH and CBL, respectively. In the second phase, the voltages BLB0 and BLB1 are equalized. As a result, the reference voltage shift can be reduced after imprint and the reference voltage can be adjusted by a reference voltage scheme with averaging multiple data. The imprint time is extended 20 times to 10 years compared with the conventional approach. Figure 57.34 shows the reference voltage-generating scheme. The voltage is generated by averaging m reference cells of the stored

Data H and n reference cells of the stored Data L. The equalize transistors are located between each BL. The distribution of the reference voltage is reduced by averaging the BL voltages of m + n reference cells. Furthermore, the reference voltage can be adjusted to the midpoint between Data H and L by optimizing the ratio between m and n after imprint.

Shiratake et al. [45] demonstrated a 32-Mbyte chain ferroelectric memory using a compact memory cell block structure that eliminates the PL area and reduces the block selector area. In addition, the group used a segment/stitch array architecture which reduces the area row decoders and plate drivers. These two techniques address the power consumption indirectly. Finally, the group introduced a low standby current bias generator that suppresses the standby current to 3 µA. The DC generator circuit is shown in Figure 57.35.

The feedback circuit enables switching between small resistance for fast response and large resistance for low standby current. The small resistance is used when the memory is in the standby mode. When the switches are turned off, the remaining charge in the resistor is distributed among the intermediate nodes causing voltage bounces. This can result in an unstable operation. Therefore, the active and standby paths are connected as seen in the figure. As a result of this symmetrical connection, the plus charge from the upper resistor in the active path compensates for the minus charge from the lower resistor when the switches are turned on and off. In this configuration, the redistribution takes less than the RC time of the small resistance.

Kawashima et al. [46] proposed a BL GND sensing (BGS) technique to increase the signal amplitude on the BLs in low-voltage FeRAMs. The sensing circuit is shown in Figure 57.36.

After the PL goes high, the negative charge sinks the polarization charge at the BL through a PMOS charge transfer (CT). Vneg will increase through charging by Ctank. The PMOS gate is biased at its threshold voltage for the source follower to keep the BL charge at the GND level. An optional inverter amplifier could be used to improve the feedback gain and the clipping of the BL at the GND voltage. The voltage difference between Vneg and xVneg creates VSA. Therefore, VSA is a function of Ctank. Thus, a smaller Ctank and a larger VSA signal can be obtained. If BL capacitance is ~1 pF (512 cells connected to BL), the VSA swing can be 2.5 times larger using BGS technique compared with the traditional high impedance sensing.

Figure 57.37 and Figure 57.38 show a hierarchical BL sensing scheme and its timing diagram [47]. The cell array block is composed of multiple subcell array blocks with folded BL structure. To reduce capacitance of SBL, each cell array of SBL is limited to 64 WL rows. Reference BL is composed from neighbor cell array block like open BL architecture, with SW1 and SW2 signals controlling the switch devices. Therefore, the reference level is immune to coupling noise (CN). Each cell data-sensing voltage is protected from CN by the unused neighbor BL. During the active time period T0, SBL and MBL are coupled by activation to Vdd or Vpp level. The WL and PL signals are activated to Vpp level of near double the Vdd level. The sensing voltage of SBL is transferred to MBL. After the sense amplifier is activated, SBSW1 and PL signals are pulled down to GND level. The SBSW2 signal is switched to Vpp level.

Fujisawa et al. [41] addressed the problem of achieving a high-speed and low-power operation in ferroelectric memories. Previous designs suffered from an excessive power dissipation due to needed refresh cycle [42,43] because of the leakage current from a capacitor storage node to the substrate where the cell plates are fixed to 1/2Vdd. Figure 57.39 shows the comparison of the power dissipation between ferroelectric memories (FeRAMs) and DRAMs. Here the power consumption of peripheral circuits is identical, but the power consumption of memory array sharply increases in the 1/2Vdd plate FeRAMs. These problems could be summarized as follows:

• The memory cell capacitance is large and therefore the capacitance of the dataline needs to be set larger to increase the signal voltage of nonvolatile data.

• The nonvolatile data cannot be read by the 1/2 Vdd subdataline (SDL) precharge technique because the cell plate is set to 1/2Vdd. Therefore, the dataline is precharged to Vdd or GND.

When the memory cells’ density rises, the number of activated datalines increases. This increases the array’s power dissipation. A selective SDL activation technique (see Figure 57.40) proposed by Fujisawa et al. [41] overcomes this problem; however, its access time is slower compared with all-SDL activation because the selective SDL activation requires a preparation time. Therefore, neither of these two tech- niques can simultaneously achieve low-power and high-speed operation.

Fujisawa et al. [41] demonstrated a low-power high-speed FeRAM operation using an improved charge-share modified (CSM) precharge-level architecture. The new CSM architecture solves the problems of slow access speed and high-power dissipation. This architecture incorporates two features that reduce the sensing period (see Figure 57.41). The first feature is the charge sharing between the parasitic capacitance of the main dataline (MDL) and the SDL. During the standby mode, all SDLs and MDLs are precharged to 1/2 Vdd and Vdd, respectively. During the read operation, the precharge circuits are all

cut off from the datalines (time t0). After the y-selection signal (YS) is activated (time t1), the charge in the parasitic capacitance of the MDL (Cmdl) is transferred to the selected parasitic capacitance of the SDL (Csdl) and the selected SDL potential is raised by charge sharing. As a result, the voltage is applied only to a memory cell intersecting selected WL and YS. The second feature is a simultaneous activation of WL and YS without causing a loss of the readout voltage. During the write operation, only data of the selected memory cell are written whereas all the other memory cells keep their nonvolatile data.

Consequently, the power dissipation does not increase during this operation. The writing period is equal to the sensing period because WL and YS can be also activated simultaneously in the write cycle.