High-Speed Circuit Design Principles:Static Frequency Divider

Static Frequency Divider

A static frequency divider (SFD) is composed of two identical latches configured as a master–slave flip-flop (MSFF), with the output, QS, inverted and fed back to the input, as in Figure 74.9 [8]. The divider is driven by an applied clock signal, and QS changes on each falling edge of the clock. There are four distinct states that the divider may occupy, arbitrarily labeled states (i) through (iv). The states are characterized by two features: the mode of operation of the latches (transparent or latched) and the outputs of the latches (high or low). These are shown in Table 74.3. On every edge of the clock the divider changes state. The slave states are identical to the master states, delayed by half of a clock cycle. To complete a cycle, the divider must undergo transitions between all four states. The maximum speed of operation of the circuit can be deter- mined by the sum of the delays of each transition.

The latches have two basic operations. Referring to Figure 74.10, the first is a current steering operation in the Q1, Q2 differential pair, moving between latched and transparent settings. The second is a voltage operation that can only occur after the current steering, changing the output voltage at QM and QS. Both operations introduce delay into the circuit and limit the maximum operating speed of the divider. Table 74.3 [8] shows that the master performs the first operation during the transition from state (ii) to state (iii) (going from transparent to latched), and performs both operations during the transition from state (iii) to state (iv). When both the master and slave are examined during the (iii)–(iv) transition, it is seen that the master will complete the transition more slowly than the slave, because it must perform both operations, whereas the slave is only performing the first operation (going from transparent to latched). Since both latches are transitioning simultaneously, and the master takes longer, only the delay contribution of the master’s transition need be considered.

Once the delay of the master in the (iii)–(iv) transition is found, it can be doubled to find the delay associated with the entire divider over the two transitions. Since the analysis is based on equal rise and fall times, the delay of the (i)–(ii), and (ii)–(iii) transitions can be assumed to be equal to the delay of (iii)–(iv) and (iv)–(i) transitions. The four transitions correspond to two input clock cycles, therefore

the maximum clock speed of operation is half their sum, which is just double the (iii)–(iv) transition delay. This corresponds to the clock-to-Q delay of the master stage.

Therefore, the signal path has been identified, as shown in Figure 74.10 and the OCTC analysis can be used to identify the time constants for each capacitor loading the device nodes. Voltage swings at each node must be determined, and large-signal device parameters can be calculated as described above. The reader should refer to Ref. [8] for the detailed analysis.

As an example of the result of such an analysis, an InP HBT-based SFD is compared with a SiGe-based SFD in Ref. [8], and the results are shown in Table 74.4. The contribution of each intrinsic circuit element can be identified in the table. It can be seen that the largest contributors to the delay for InP are RL and CCB and for SiGe, RL and CBE.

Thus, the RLCCB and RLCBE time constants must be the dominant ones. This indicates that the performance can be improved if the logic swing could be reduced or the tail current increased. The logic swing is limited by the noise margin and cannot be reduced below roughly

Here, the indirect importance of REX can be seen; REX must be minimized to reduce the logic voltage swing without compromising noise margin.

The current is limited by the maximum device current density, JMAX, generally set by the Kirk effect, which increases collector transit delays at high current density. This is determined by the saturated drift velocity, vsat, the collector–base voltage, VCB, the junction potential, f, and the collector thickness, TC.

VCB is limited by breakdown and cannot be arbitrarily increased. But the collector thickness can be reduced. When CCB and JMAX are considered, we find that

where AC and AE are collector and emitter areas, respectively. So, it is seen that the collector capacitance charging time is reduced by decreasing the collector thickness and increasing the current [10]. Unfortu- nately, decreasing CBE is not simple as the depletion thickness and doping are critical to the conduction band grading at the heterointerface and thus injection efficiency of the junction. But, larger current will reduce the time constant as well.

The time constant technique is also useful for estimating the optimum areas of the emitter follower and differential pair transistors since their respective contributions to total delay can be separated [8].